Intel Corporation

Qualcomm Incorporated

Hasnain Lakdawala

Ashoke Ravi

Ofir Degani

Georgios Yorgos Palaskas

Krishnamurthy Soumyanath

Ojas Choksi

Paolo Madoglio

Masoud Sajadieh

Soumyanath Krishnamurthy

Zdravko Boos

Stefano Pellerano

Francesco Gatta

Bernd-Ulrich Klepser

Ahmed Abbas Mohamed Helmy

Bin Fan

Bassel Hanafi

Stewart S Taylor

Hiroyuki Ito

Greg F Taylor

Arijit Raychowdhury

Razak Hossain

Faramarz Sabouri

Marco Zanuso

Masoud Moslehi Bajestan

Sherif Abdelhalem

Hyung Seok Kim

Balasubramanian Ramachandran

Yee (William) Li

Yee W Li

Stefan H Andersson

Rotem Banin

Aleksandar Miodrag Tasic

Prashanth Akula

Wei Zhuo

Benjamin Jann

Eshel Gordon

Rahul Karmaker

Joung Won Park

Kyle David Holland

Janakiram Ganesh Sankaranarayanan

Prakash Thoppay Egambaram

Jang Joon Lee

Ketan Humnabadkar

Marian K Verhelst

Yorgos Palaskas

Mehran Bakhshiani

Andrea Fenaroli

Tony Chang

Degani Ofir

Alpman Erkan

Julia H Lu

Gordon Eshel

Simone Gambini

Itshak Hod

Pukar Malla

Abhishek Ananthrao Kulkarni

Shankar Guhados

Sophia Maerkovich

Certain aspects of the present disclosure generally relate to techniques and apparatus for operating a wireless receiver of the apparatus in a high linearity mode. An example method includes operating the apparatus in a first mode with transmission of a plurality of transmit signals. The method also includes attenuating a received signal via an attenuator while operating the apparatus in the first mode. The method further includes amplifying the attenuated signal with an amplifier while operating the apparatus in the first mode. For certain aspects, the method further involves operating the apparatus in a second mode, bypassing the attenuator while operating the apparatus in the second mode, and amplifying the received signal with the amplifier while operating the apparatus in the second mode.

High linearity modes in wireless receivers

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

Programmable baseband filter for selectively coupling with at least a portion of another filter

Techniques and apparatus are described for reducing power consumption when performing wireless communications by dynamically changing the frequency of a local oscillator signal for a radio frequency (RF) downconversion circuit, based on signal conditions. An example method includes receiving an RF signal and downconverting the RF signal using an oscillating signal with a first frequency at a first time. The method also includes switching to downconverting the RF signal using the oscillating signal with a second frequency, based on a property associated with the RF signal at a second time. The second frequency is a subharmonic of the first frequency.

Dynamic subharmonic mixing for power reduction in wireless communications

An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.

Frequency doubler with duty cycle correction

An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.

Calibration of sampling-based multiplying delay-locked loop (MDLL)

Certain aspects of the present disclosure provide a local oscillator (LO) for wireless communication. In some examples, the LO is configured to generate an LO signal by inverting, by a first inverter, a first signal to generate a second signal having a first frequency, the first signal being an oscillating signal. In some examples, the LO is configured to control, using a third signal having a second frequency, a first switch receiving the second signal. In some examples, the LO is configured to control, using a fourth signal having the second frequency, a second switch receiving the second signal, wherein the fourth signal is a complement of the third signal and wherein the second frequency is one-half the first frequency.

Local oscillator (LO) for wireless communication

This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

Direct digital frequency generation using time and amplitude

Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator.

Low-noise amplifier (LNA) with capacitive attenuator

Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.

Scalable stochastic successive approximation register analog-to-digital converter

A device and method for amplifying signals is provided. The device can have an input to receive an input signal having a first desired signal on a first carrier, a second desired signal on a second carrier, and one or more interfering signals. The device can have a first carrier aggregation (CA) chain for use with the first desired signal and a second CA chain for use with the second desired signal. The first and second CA chains can be coupled to the input. The first and second CA chains can have a plurality of transconductance stages. Each of the transconductance stages can be configured as a high impedance stage or a low impedance stage. The transconductance stages can be selectively activated to incrementally adjust the transconductance, and therefore the input impedance, of each of the CA chains.

Wideband high linearity LNA with intra-band carrier aggregation support

This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive a phase data information from a baseband processor and to provide a first modulation signal for generating a wireless signal, a detector configure to receive the first modulation signal and provide an indication of nonlinearities of the DTC, and a pre-distortion module configured to provide pre-distortion information to the DTC using the indication of nonlinearities.

Feedback calibration of digital to time converter

The disclosure is directed to a circuit arrangement and method that provide efficient concurrent transmit and receive, transmit only and receive only of wireless signals. In one implementation, a circuit arrangement is provided that incorporates uses a single antenna to achieve concurrent transmit and receive, transmit only and receive only of wireless signals. A dual amplifier structure may be provided, and at least one of the amplifiers associated with the dual amplifier structure is amplitude tunable in order to ensure that each amplifier of the dual amplifier structure provides substantially the same or the same signal amplification. Unwanted transmit signals detected by a receiving circuit arrangement may be used to cause a processor to generate a digital code word that is used to modify a signal amplification provided by at least one of the amplifiers associated with the dual amplifier structure.

Concurrent transmit and receive

An apparatus including: a first switch configured to provide a feed-forward path at an input of a first amplifier of a plurality of amplifiers coupled together at a single port, the feed-forward path configured to substantially reduce a leakage current into an input of a second amplifier of the plurality of amplifiers.

Input switch leakage compensation

An apparatus including: at least one differential amplifier configured to amplify a radio frequency signal; a mixer configured to mix the radio frequency signal from the at least one differential amplifier with a local oscillator signal; and a low-pass filter coupled to the mixer, the low-pass filter includes a capacitor and at least one variable resistor configured to tune the low-pass filter.

Sawless architecture for receivers

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Beaverton, OR, United States of America

Hasnain Lakdawala