Northrop Grumman Systems Corporation

Trw Limited

Harvey Newell Rogers

Michael Edward Barsky

Richard Lai

Yaochung Chen

Mark Kintis

Dean Tran

William L Jones

Raffi N Elmadjian

Vladimir Medvedev

Edwin W Sabin

A method () for etching a through via () on a wafer () of semiconductor material (), wherein the wafer () has a front side surface () and a backside surface (), is described. A layer of photoresist material () is applied to the backside surface (). The layer of photoresist () is then exposed to a light source through a mask having a pre-selected pattern, wherein the developed photoresist is removed to form at least one via () in the remaining photoresist layer (). The remaining photoresist layer () is then baked in order to form a hardened, remaining photoresist layer (). The semiconductor material 102 adjacent to the at least one via () is then gas plasma etched to form a through via () between the backside surface () and the front side surface (). The hardened, remaining photoresist layer () is then removed and a layer of conductive material () is then applied to the surface of the through via () to establish electrical connectivity between the backside surface () and the front side surface ().

Wafer etching techniques

An inexpensive package for a semiconductor chip () that incorporates a stress relief buffer () between a side of the chip and the metal carrier layer () to absorb thermally induced stress produced by significantly different rates of thermal expansion of the wafer and the metal carrier. The buffer () is formed by a polymer that is flexible and can be etched, contains a coefficient of thermal expansion that does not significantly differ from that of the chip and/or a combination of CET and elasticity that retains a physical connection with the side of the chip and the metal carrier over the temperature range of operation anticipated for the chip. Polyimide or paraylene are preferred examples. Vias () extend through the buffer to place the metal carrier electrically in common with the metal layer () found on the back surface of the wafer so that an electrical ground applied to the metal carrier layer () may extend through to that surface.

Inexpensive wafer level MMIC chip packaging

Apparatuses ( ), and methods of using same, for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers (W) using a non-crystallographic and uniform etching process, are described. The apparatuses ( ) include a fixture ( ) having a plurality of horizontal receptacles ( ) for receiving the semiconductor wafers (W). The loaded fixtures ( ) are then immersed into an etchant solution ( ) that is capable of isotropically removing a layer of semiconductor material from the backside surface of the semiconductor wafers (W). The etchant solution ( ) is preferably heated to about 40&deg; C.-50&deg; C. and constantly stirred with a magnetic stirring bar ( ). Once a sufficient period of time has elapsed, the thinned semiconductor wafers (W) are removed from the etchant solution ( ). The apparatuses ( ) are capable of simultaneously thinning several semiconductor wafers (V) down to a final thickness of about 25 &mgr;m.

Wafer thinning techniques

A method is provided for backside processing a semiconductor wafer ( ) including applying a polymer based protective coating ( ) on the wafer, depositing a barrier layer of ceramic ( ) on the protective coating, and coating the ceramic layer with a thermoplastic based adhesive ( ). Thereafter, the wafer ( ) is bonded to a perforated substrate ( ) and then lapped and polished to a desired thickness and patterned with an etch mask. A high temperature plasma etching process is then used to etch via holes in the wafer ( ). After etching and subsequent backside processing, the adhesive layer ( ) is dissolved in acetone to separate the wafer ( ) from the substrate ( ). The protective coating ( ) is then dissolved with a solvent to separate the ceramic layer ( ) from the finished wafer ( ).

Wafer adhesive for semiconductor dry etch applications

A photosensitive photoresist material which is effective for use as an ion etch barrier layer after patterning. The photoresist composition includes the reaction product of a compound having the general formula R.sub.1 --COO--(CH.sub.2).sub.n --O--R.sub.2 and a silylating agent.

Growing community of inventors

Playa Del Rey, CA, United States of America

Harvey Newell Rogers