Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Haruyuki Sorada

Takeshi Takagi

Akira Asai

Akira Inoue

Takumi Mikawa

Yoshio Kawashima

Yoshihiro Hara

Yoshihiko Kanzawa

Teruhito Ohnishi

Junko Iwanaga

Kiyoshi Morimoto

Kiyoyuki Morita

Takahiro Kawashima

Tohru Saitoh

Gaku Sugahara

Shigeo Yoshii

Yukio Hayakawa

Atsushi Himeno

Satoru Fujii

Chiaki Kudou

Takeki Ninomiya

Tsutomu Kiyosawa

Yasuyuki Yanase

Kiyotaka Tsuji

Tsuneichiro Sano

Kenji Tominaga

Kazuhiro Kagawa

Kouji Katayama

A semiconductor device includes: semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the gate insulating layer positioned on the semiconductor layer; a gate electrode positioned on the gate insulating layer and having a first surface in contact with the part of the gate insulating film and a second surface opposite to the first surface; an interlayer insulating layer covering the gate electrode; and an electrode in contact with the impurity region. The gate electrode has a recess at a corner in contact with the second surface, in a cross section of the gate electrode perpendicular to a surface of the semiconductor layer. A cavity surrounded by the gate electrode and the interlayer insulating layer is positioned in a region including at least a part of the recess.

Semiconductor device and method for fabricating the same

A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure.

Nonvolatile memory element, nonvolatile memory device, and manufacturing method for the same

A semiconductor device includes: a substrate with an off-angle; an SiC layer provided on a principal surface of the substrate, including an n type drift region, and having a trench whose bottom is located in the drift region; and a gate electrode provided in the trench in the SiC layer. In the trench in the SiC layer, a first angle formed by at least part of a first sidewall on an off-direction side and the principal surface of the substrate is an obtuse angle, and a second angle formed by at least part of a second sidewall opposite to the first sidewall and the principal surface of the substrate is an acute angle, in a cross section parallel to a direction of a normal line to the principal surface of the substrate and a direction of a c-axis of the substrate.

Semiconductor device and method for manufacturing same

Each of the step of forming a first variable resistance layer () and the step of forming a second variable resistance layer () includes performing a cycle once or plural times, the cycle consisting of a first step of introducing a source gas composed of molecules containing atoms of a transition metal; a second step of removing the source gas after the first step; a third step of introducing a reactive gas to form a transition metal oxide after the second step; and a fourth step of removing the reactive gas after the third step. The step of forming the first variable resistance layer () is performed in a state in which the substrate is kept at a temperature at which a self-decomposition reaction of the source gas does not occur. One or plural of conditions used for forming the second variable resistance layer () is/are made different from the one or plural conditions used for forming the first variable resistance layer (), the conditions being the temperature of the substrate, an amount of the introduced source gas and an amount of the introduced reactive gas.

Manufacturing method of non-volatile memory device

A method of manufacturing a nonvolatile memory device that is a variable resistance nonvolatile memory device, which has good consistency with a dual damascene process that is suitable for the formation of fine copper lines and which enables large capacity and high integration. This method includes: forming a variable resistance element, a contact hole and a line groove; and forming a current steering layer of a bidirectional diode element above interlayer insulating layers and a variable resistance layer to cover the line groove without covering a bottom surface of the contact hole.

Nonvolatile memory device manufacturing method

Provided are a nonvolatile memory device which can suppress non-uniformity in initial breakdown voltages among nonvolatile memory elements and prevent reduction of yield, and a manufacturing method thereof. The nonvolatile memory device includes a nonvolatile memory element () having a stacked-layer structure in which a resistance variable layer () is parallel to a main surface of a substrate () and is planarized, and a plug () electrically connected to either a first electrode () or a second electrode (), and an area of an end surface of a plug () at which the plug () and the nonvolatile memory element () are connected together, the end surface being parallel to the main surface of the substrate (), is greater than a cross-sectional area of a cross-section of a first transition metal oxide layer () which is an electrically-conductive region, the cross-section being parallel to the main surface of the substrate ().

Nonvolatile memory device and manufacturing method thereof

A variable resistance non-volatile storage device includes: a first line which includes a barrier metal layer and a main layer, and fills an inside of a line trench formed in a first interlayer insulating layer; a first electrode covering a top surface of the first line and comprising a precious metal; memory cell holes formed in a second interlayer insulating layer; a variable resistance layer formed in the memory cell holes and connected to the first electrode; and second lines covering the variable resistance layer and the memory cell holes, wherein in an area near the memory cell holes, the main layer is covered with the barrier metal layer and the first electrode in an arbitrary widthwise cross section of the first line.

Non-volatile storage device and method for manufacturing the same

A manufacturing method includes forming, on a substrate, lower layer copper lines each being shaped into a strip, forming electrode seed layers each being shaped into a strip, on the respective lower layer copper lines using electroless plating, forming an interlayer insulating layer above the electrode seed layers, forming, in the interlayer insulating layer, memory cell holes, penetrating through the interlayer insulating layer and extending to the electrode seed layers, forming noble metal electrode layers on the electrode seed layers exposed in the respective memory cell holes using the electroless plating, forming, in the respective memory cell holes, variable resistance layers connected to the noble electrode layers, and forming, above the interlayer insulating layer and the variable resistance layers, upper layer copper lines each being shaped into a strip, connected to a corresponding one of the variable resistance layers, and crossing the lower layer copper lines.

Variable resistance nonvolatile memory device and method of manufacturing the same

The semiconductor deviceof this invention includes: a semiconductor layerarranged on the principal surface of a substrateand made of a wide bandgap semiconductor; a trenchwhich is arranged in the semiconductor layerand which has a bottom and a side surface; an insulating regionarranged on the bottom and side surface of the trench; and a conductive layerarranged in the trenchand insulated from the semiconductor layerby the insulating region. The insulating regionincludes a gate insulating filmarranged on the bottom and the side surface of the trenchand a gaparranged between the gate insulating filmand the conductive layerat the bottom of the trench. The gate insulating filmcontacts with the conductive layeron a portion of the side surface of the trenchbut does not contact with the conductive layerat the bottom of the trench. The thickness of the insulating regionmeasured from the bottom of the trenchthrough the lower surface of the conductive layeris greater around the center of the trench than beside its side surface.

Semiconductor device and method for fabricating the device

A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

FINFET-type semiconductor device and method for fabricating the same

A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

CMOS and HCMOS semiconductor integrated circuit

A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation regionfor partitioning the principal face into a plurality of device active regions; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regionsamong the plurality of device active regionsof the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions, each of the device active regionson which the epitaxial layer is formed and each of the device active regions Aon which the epitaxial layer is not formed. Step (A) includes step (a1) of forming, in the isolation region, a plurality of dummy regionssurrounded by the device isolation structure (STI), and step (B) includes step (b1) of growing a layer of the same material as that of the epitaxial layer on selected regions among the plurality of dummy regions

Semiconductor manufacturing method and semiconductor device

A semiconductor device according to this invention includes: a first insulating layer (); a first body section () including an island-shaped semiconductor formed on the first insulating layer; a second body section () including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section () formed on the first insulating layer to interconnect the first body section and the second body section; a channel region () formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode () formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

Strained channel finFET device

The present invention provides a semiconductor device comprising: a semiconductor layer (); a gate electrode () formed on the semiconductor layer () via a gate insulation film (); and a first insulation film () formed at one or more of sidewalls of the semiconductor layer (), the gate insulation film () and the gate electrode (); wherein the first insulation film () overlies a part of the gate insulation film () surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

Growing community of inventors

Hirakata, Japan

Haruyuki Sorada