Hitachi, Ltd.

Haruyuki Nakayama

Takeshi Aimoto

Hiroshi Iwamoto

Shoichi Murase

Takehisa Hayashi

Hidenori Inouchi

Satoshi Yoshizawa

Hideki Murayama

Kazuhiro Hashimoto

Hiroshi Ohguro

Kenji Nakajima

Shinichi Tanabe

Hiromichi Yamada

Ryo Fujita

Teppei Hirotsu

Kotaro Shimamura

Dai Fujii

In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.

Logic compound method and logic compound apparatus

A data communication system for a computer system in which a plurality of computers are mutually connected includes: a plurality of computers each having an area to store a command to execute a data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the plurality of computers; and a transmission permitting component, connected between the switch circuit and one of the plurality of computers, for outputting a signal to permit the data transmission from such one computer to such another computer; a communication component for transmitting the data received from such one computer by outputting the transmission permission signal from the transmission permitting component to such another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from such one computer to such another computer; and a communication control component to abandon the data that is subsequently received from such one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases such another computer, thereby disconnecting such one computer and such another computer. When reception commands prepared in the buffer area of such another computer are perfectly used, such another computer abandons the packet which does not include the flag to instruct the continuous reception.

Network for mutually connecting computers and communicating method using

A data communication system for a computer system in which computers are mutually connected includes: each computer having an area to store a command to execute data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the computers; and a transmission permitting component, connected between the switch circuit and one of the computers, for outputting a signal to permit the data transmission from one computer to another computer; a communication component for transmitting the data received from one computer by outputting the transmission permission signal from the transmission permitting component to another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from one computer to another computer; and a communication control component to abandon the data that is subsequently received from one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases another computer, thereby disconnecting one computer and another computer. When reception commands prepared in the buffer area of another computer are perfectly used, another computer abandons the packet which does not include the flag to instruct the continuous reception.

A large-scaled interconnection switch in which a plurality of data processors are interconnected to perform data transfer between one another. The switch includes communication controllers, one provided for each of the plurality of data processors, divided into groups, for controlling communication between the data processors. Each group of communication controllers is connected by a signal line having a multiple bit width. A switch arbiter for arbitrates switch setting requests for interconnection of the data processors from the communication controllers to output a switch setting control signal. The switch also includes bit slice switches having a predetermined bit division count and to which respective/output signal lines are connected which bit-divide input/output signals of the communication controllers. The bit slice switch receives a switch setting control signal from the switch arbiter and transfers data from a transmission data line from a communication controller to a receiving data line to the communication controller on the basis of the switch setting control signal.

Large scale interconnecting switch using communication controller groups

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Washington, DC, United States of America

Haruyuki Nakayama