Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Hitachi, Ltd.

Nec Corporation

Haruo Yamashita

Kazuyuki Tajima

Yuji Takizawa

Tomohiro Ishihara

Masaaki Kawai

Tomohiro Shinomiya

Takaaki Wakisaka

Hisako Watanabe

Ryuichi Kondo

Hidetoshi Naito

Toshiyuki Sudo

Masatake Miyabe

Atsuki Taniguchi

Nagao Shimada

Kazuo Yamaguchi

Hiroyuki Sato

Junichi Tamura

Shinichiro Saito

Motoo Nishihara

Hiromi Ueda

Kazuo Iguchi

Masaki Hirota

Takatoshi Kurano

Jinichi Yoshizawa

Masamichi Kasa

Tomoyuki Ohtsuka

Hideo Tatsuno

Hiroomi Tateishi

Ikuo Tokizawa

Masayoshi Sekido

Satomi Ikeda

Xiping Lin

Yuji Takigawa

The present invention provides a network relay apparatus capable of assuring the prevention of occurrence of order reversion of packets within flows and shifting a packet distribution destination according to load information. The network relay apparatus includes: a packet distribution processor for distributing input packets to thereby achieve load dispersion of packet processing; a statistical information collector for regularly collecting load conditions of respective packet processors; and a distribution information holder for retaining information for specifying the packet distribution destinations upon distribution of the packets. Information about the load conditions of the respective packet processors are compiled and distributed to the packet processor smallest in load. Timing provided to change the packet distribution destination is assumed to be given when a processing waiting queue does not include a packet corresponding to its flow.

Network relay apparatus and packet distribution method

A method for time-division multiplexing including steps of generating a plurality of first signals and a plurality of second signals to which specific pulse trains for frame synchronization are allocated respectively; generating low speed signals of plural channels including the first and second signals and transmission signals; a conversion step; and time-division multiplexing the low speed signals after the conversion step, thereby obtaining high speed signals. When applied to SDH, for example, the first and second signals may be A1 bytes and A2 bytes respectively, and the transmission signals may ho payload signals. According to one aspect of the invention, at the conversion step, the first and second signals in each channel are panty convened into either of '1/0' alternating signals and '0/1' alternating signals. Consequently, it becomes possible to reduce the number of successive same code and to diminish the deviation of the mark rate.

Method for time-division multiplexing

A subscriber-line-terminating apparatus for dynamically allocating band portions to a plurality of terminal apparatuses includes an in-buffer-information-amount receiving unit for receiving an in-buffer-information amount from each of the terminal apparatuses; an insufficient-band-computing unit for computing an insufficient band portion required by each of the terminal apparatuses; an in-buffer-information-amount-proportional-band-allocating unit for allocating a band portion corresponding to the in-buffer-information amount to each of the terminal apparatuses and a past-use-band-allocating unit for allocating a past-use band part to each of the terminal apparatuses as a past-use band portion based on a first past-use band variable of the terminal apparatus.

Dynamic band-allocating subscriber-line-terminating apparatus

An optical switch device improving a yield and compact and excellent in expandability of optical incoming/outgoing ports, comprised of: a plurality of planar switch modules arranged in the horizontal direction and stacked in the vertical direction; and a coupler switch module, arranged in the vertical direction along each one side of the planar switch module, for selectively coupling the plurality of optical paths formed on one planar switch module and a plurality of optical paths formed on another planar switch module.

Optical switch device

In a system where a plurality of terminal units are connected to a network unit via an optical transmission line and packets are transmitted in units of cells according to polling information, polling request information including the number of variable-length packets stored in the buffer of each of the terminal unit, the number of cells composing each variable-length packet and the number of remaining cells of a packet being read is created, polling information corresponding to a time slot allocated according to the polling request information is transmitted from the shared band control unit of the network unit, and bands are allocated to the plurality of terminal units.

Band allocation method and transmission system for transmitting variable-length packets

A fault recovery system of a ring network based on a synchronous transport module transmission system, having a fault data writing unit for writing, when an input fault is detected by a node, fault data in a predetermined user byte in an overhead of a frame flowing through both a working line and a protection line running in opposite directions to each other. By detecting the fault data in a supervision node or a node just before the fault position, the supervision node or the node just before the fault position executes a loopback operation.

Fault recovery system of a ring network

Disclosed is a clock distributing apparatus for distributing clock signals with a desired phase to each of devices provided between a clock generating section (10) for generating clock signals and a plurality of devices (30) for receiving the clock signals. A delay generating section (21) generates a plurality of delay clock signals by imparting a plurality of delay quantities to the clock signals from the clock generating section. A clock distributing section (22) has a plurality of input terminals corresponding to the plurality of delay clock signals and a plurality of output terminals corresponding to the respective devices. The clock distributing section (22) distributes desired delay clock signals to one or more output terminals by selecting the input terminals corresponding to the desired delay clock signals.

Clock distributing method and apparatus

According to the present invention, when a current system is switched to a spare system in a transmission system in an asynchronous transfer mode, empty cells transmitted in the current and spare systems are detected, and thereby a timing for switching the current system to the spare system is determined. When no phase difference is existent between the current and spare systems, an empty cell is detected in both the current and spare systems at the same time. Therefore, the current system is switched to the spare system, when an empty cell is detected in both the current and spare systems at the same time. When a shade difference is existent, if an empty cell is detected either in the current or spare systems, another empty cell is inserted in to the systems. Then, the data of the empty cell in a spare system is saved. After the empty cell in a current system passes, the current system is switched to the spare system. When a phase difference of at least one cell is existent, and if an empty cell comes earlier in current system, empty cell are kept inserted form when the empty cell is detected in the current system until an empty cell is detected in the spare system. After that, the current system is switched to the spare system. When an empty cell comes earlier in a spare system, the data of the cell in the spare system is saved from when the empty cell is detected until an empty cell is detected in the current system. After that, the current system is switched to the spare system.

Apparatus and method for non-stop switching in asynchronous transfer mode

In a cross-connect apparatus for use in selectively connecting a plurality of input transmission paths to a plurality of output transmission paths, each of the input and the output transmission paths is divided into first through m-th groups each of which is composed of first through n-th transmission paths, first through m-th elementary switch modules are located between the input and the output transmission paths, n in number, of the first through the m-th groups and are connected to a connection switch module through first to m-th input internal path groups each of which is composed of n internal paths and which are extended into first through m-th switch units each of which has input terminals, n(m-1) in number, and output terminals, n in number, where n and m are natural numbers. An i-th one of the switch units in the connection switch module is connected to the input path groups, (m-1) in number, except an i-th internal path group, where i is a natural number between unity and m, both inclusive. The output terminals of the i-th switch unit is connected to an i-th one of the elementary switch modules through an i-th one of output internal paths. This structure serves to avoid an unnecessary detour route in the cross-connect apparatus.

Cross-connect apparatus capable of avoiding a superfluous detour route

A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

One bit error correction method having actual data reproduction function

Asynchronous signal extracting circuit

When input signals from a plurality of input ports are selected and are inserted into the time slots to be output from a single output port and to insert respective signal data into time slots in synchronization with a synchronizing signal, the apparatus is so constructed that selector units (5-i) are provided to correspond to input ports (1-i), and a synchronizing signal generating unit (4) is provided to output, synchronously, a synchronizing signal and selecting signal information for designating a selector unit (5-i); the selector unit (5-i) being provided with a determining unit (6) for determining whether or not the selecting signal information designates the selector.

Input-output signal control apparatus

A synchronous circuit includes a first circuit block operating in synchronism with a first clock signal, and a second circuit block operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal. The first circuit block includes a frame synchronizing circuit for detecting a synchronous pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part. The first circuit block includes a synchronizing unit for generating, from the synchronous pattern, a synchronizing control signal for synchronizing the operation of the second circuit block with the operation of the first circuit block. The first circuit block includes a pulse generator for generating a first frame pulse signal from the first clock signal. The second circuit block includes an information part detecting unit for generating a second frame pulse signal having a frequency lower than that of the first frame pulse signal from the second clock signal and the synchronizing control signal, the first frame pulse signal being synchronized with the beginning of the information part.

Synchronization circuit for establishing frame synchronism using

A cross-connection apparatus for B-ISDN includes plural interface units, multiplexers, virtual path identifier (VPI) conversion tables, demultiplexers, and loop-back units and a switch unit. The interface unit has a reception port for receiving an ATM cell or inserting a monitor cell, and a transmission port for transferring the ATM cell or extracting the monitor cell; The multiplexer is operatively connected to corresponding interface unit for multiplexing the monitor cell; The VPI conversion tables is operatively connected to corresponding multiplexer for converting the VPI to change a transmission route of the monitor cell; The switch unit is operatively connected to the VPI conversion tables for switching the transmission route of the monitor cell based on the VPI; The demultiplexer is operatively connected to the switch unit for demultiplexing the monitor cell and transferring the monitor cell to the transmission port; The loop-back unit is operatively connected to corresponding interface unit for changing the transmission route so as to transfer the monitor cell to the same interface unit which the monitor cell is inserted, and as a result, the apparatus can be monitored by comparing the inserted monitor cell with the extracted monitor cell in the same interface unit.

Growing community of inventors

Kawasaki, Japan

Haruo Yamashita