Seiko Epson Corporation

Haruo Nishida

Takuya Ishida

Yoshiyuki Kamihara

Nobuharu Kobayashi

A transfer controller (or a host controller) issues IN tokens to a plurality of USB devices connected to USB and including first and second USB devices. When data including destination information which specifies the second USB device as a destination has been received in response to an IN token issued to the first USB device, the transfer controller issues an OUT token to the second USB device and transmits the received data from the first USB device to the second USB device. The transfer controller issues an IN token to at least one of the USB devices which has declared itself to be a local area network (LAN) node.

USB data transfer control device including first and second USB device wherein destination information about second device is sent by first device

A macro block MBincluding a physical-layer circuit PHY for communications performs transmission and reception processing to and from a macro block MBat a clock frequency CF. A test circuit TC includes a test transmission buffer TXB that stores a transmission data signal from a test input terminal TPI at a frequency CFthat is lower than the frequency CF, and a test reception buffer RXB that outputs a reception data signal to a test output terminal TPO at a frequency CFthat is lower than the frequency CF. After the transmission buffer TXB has stored the transmission data signal from the terminal TPI at the frequency CF, it outputs the stored transmission data signal to the MBat the frequency CF. After the reception buffer RXB has stored the reception data signal from the MBat the frequency CF, it outputs the stored reception data signal to the terminal TPO at the frequency CF

Integrated test circuit, a test circuit, and a test method for performing transmission and reception processing to and from a first and a second macro block at a first frequency

A test circuit comprises a selector SELhaving a first input to which signals MOUT from a macro block MBare input and a second input to which test input signals TINand TINfor a macro block MBare input, and a selector SELhaving a first input to which a signal SQ from the SELis input and a second input to which a signal MOUT from the MBis input. In a first test mode in which the MBis tested, the SELoutputs the signals MOUT from the MBto a first input of the SEL, and the SELoutputs the signal SQ from the SELto the MB. In a second test mode in which the MBis tested, the SELoutputs the test input signals TINand TINfor the MBto the MB, and the SELoutputs the signals MOUT from the MBas a test output signal TOUT for the MB

Test circuit, integrated circuit, and test method

A macro cell creating method capable of accurately calculating the delay values regarding input/output terminals of a macro cell and efficiently designing a high-speed macro cell. The macro cell creating method includes a first step for creating a frame of a macro cell based on a size estimate of a circuit, a second step for disposing provisional external input/output terminals on the frame of the macro cell based on input/output terminal information of the circuit, a third step for adding connection information of the provisional external input/output terminals with actual input/output terminals to circuit connection information, a fourth step for disposing basic function cells based on the circuit connection information, a fifth step for wiring the basic function cells, a sixth step for deleting wired lines between the provisional external input/output terminals and the actual input/output terminals, and a seventh step for creating macro cell layout data.

Growing community of inventors

Sapporo, Japan

Haruo Nishida