Seiko Instruments Inc

Kosaku & Co., Ltd.

Haruo Konishi

Masanori Miyagi

Yoshikazu Kojima

Yutaka Saitoh

Kazuaki Kubo

Toru Machida

Toru Shimizu

Tetsuya Kaneko

Kazuhiro Fukuoka

Fumiyasu Utsunomiya

Jun Osanai

Yukio Suzuki

Naoto Saitoh

Masanao Hamaguchi

Keiki Kiyohara

Isao Miyatake

Saburo Yonekura

A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.

Semiconductor device and manufacturing method thereof

In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region,having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region,having a second impurity concentration determined by doping an impurity to the region selected by a pattern,of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region,having the first impurity concentration and the channel region,having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.

A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.

MISFET semiconductor integrated circuit device

To obtain an extremely small constant current with high accuracy, a constant current circuit comprises a first constant-current source for producing a first constant current, a second constant-current source connected to the first constant-current source for producing a second constant current having a different value from that of the first current, and an output terminal from which a third constant current equal to the difference between the first and second constant currents is output, such that the third constant current having an extremely small value may be produced without the use of a constant current source capable of producing an extremely small constant current value. The first and second constant current sources may be connected in series with the output terminal connected therebetween, or in parallel through a current mirror circuit. In addition, the constant current circuit can be provided in a timer circuit to produce a very long constant time signal with great stability. In one embodiment, such a timer circuit further includes a capacitor connected to the output terminal for receiving the third constant current and accumulating charge, a reference voltage generator for producing a reference voltage, and a voltage comparator for comparing the voltage of the capacitor with the reference voltage.

Semiconductor integrated circuit device for obtaining extremely small

A semiconductor integrated circuit comprises a semiconductor substrate of a first conductivity type, at least one electrically erasable floating gate type semiconductor non-volatile memory transistor disposed on a surface of the semiconductor substrate, a well region of a second conductivity type formed in the surface of the semiconductor substrate, and a program voltage switching transistor of the first conductivity type disposed in the well region. A field insulation film is disposed on the surface of the semiconductor substrate. A field dope region of the first conductivity type is provided beneath the field insulation film. The field dope region preferably has an impurity concentration higher than an impurity concentration of the semiconductor substrate. By this construction, current leakage is prevented at the time when a high voltage occurs such as, for example, when performing a writing operation with respect to EEPROM.

Semiconductor integrated circuit

A semiconductor integrated circuit which operates with a single power source and has a high-tension circuit for generating a voltage higher than a power voltage and for logically processing is enabled to operate at a low power voltage by reducing the current consumed in the high-tension circuit. The semiconductor integrated circuit of the present invention comprises a block transistor 1, Vcc line circuit 2, Vpp line circuit 3 and gate potential varying circuit 4. Gate potential of the block transistor 1 is controlled by the gate potential varying circuit 4. The gate potential varying circuit 4 outputs a signal for controlling the gate potential of the block transistor 1.

Integrated circuit for operation with plural supply voltages

The nonvolatile memory includes a voltage booster and a supply voltage detection circuit, which is powered only when the voltage booster is operated so as to limit current consumption of the supply voltage detection circuit to substantially only leakage current during a non-operation period of the booster.

Semiconductor nonvolatile memory device integrated with booster

An electroless Pb-Sn alloy plating bath composition is obtained by mixing at least one of methane sulfonic acid, 1-hydroxyethane-1, 1-diphosphoric acid and a salt of 1-hydroxyethane-1, 1-diposphoric acid, compounds for forming Pb-Sn alloy and a reducing agent.

Electroless Pb-Sn alloy plating bath composition

An electroplating bath for the formation of a tin-cobalt, tin-nickel, or tin-lead binary alloy coating is produced by mixing (a) as alloy coating-forming agent a tin salt and one member selected from the group consisting of a cobalt salt, a nickel salt, and a lead salt, (b) 1-hydroxyethane-1,1-diphosphoric acid and/or a salt thereof, (c) methanesulfonic acid and/or an alkali salt thereof, and (d) an electroconductive salt. A coating formed by electroplating using the bath is stable and excellent in gloss.

Growing community of inventors

Chiba, Japan

Haruo Konishi