Fujitsu Corporation

Fujitsu Hitachi Plasma Display Limited

Haruo Koizumi

Makoto Onozawa

Yoshikazu Kanazawa

Tomokatsu Kishi

Yoshinori Okada

Masami Aoki

Shigeharu Asao

Shigetoshi Tomio

Toyoshi Kawada

Hideaki Ohki

Takumi Miyashita

Tetsuya Sakamoto

Takeshi Kuwahara

Masatoshi Hira

Toshiyuki Teramoto

A power module is provided which includes: a power-supply voltage terminal for inputting a power-supply voltage; a ground terminal; a first voltage terminal; a second voltage terminal; a first to a third switch; and a first to a third amplification circuit which amplify control signals for controlling the first to the third switch, respectively. The first switch is connected between the power-supply voltage terminal and the first voltage terminal. The second switch is connected between the first voltage terminal and the ground terminal. The third switch is connected between the second voltage terminal and the ground terminal.

Power module and display device

A predrive circuit, a drive circuit and a display device which are capable of driving output elements so as to transmit control signals stably even when reference potentials generated on the output elements side turn to high voltage. A first level shift circuit outputs a flow signal which is an input signal according to a first level shift potential. A second level shift circuit outputs a flow signal which is the flow signal output from the first level shift circuit, according to a second reference potential. A level shift power supply circuit supplies the level shift potential based on a prescribed power supply voltage and the second reference potential to the first level shift circuit and the second level shift circuit.

Predrive circuit, drive circuit and display device

A pre-drive circuit having low deviation of timing of a high level and a low level output voltages is disclosed. A plurality of drive systems are comprised, each having an input amplifier circuits for amplifying input voltages input to input voltage terminals, high level shift circuits for shifting signal levels output from the input amplifier circuits, and output amplifier circuits for amplifying shift signals output from the high level shift circuits, and each drive system has the same constitution.

Pre-drive circuit, capacitive load drive circuit and plasma display apparatus

A circuit board assembly has a flat coil element mounted on a circuit board so that an electric power loss is not generated even when the flat coil element is mounted to the circuit board together with a circuit part having a large heat sink. A module mounted on the circuit board has an electronic circuit device and a heat radiator attached to the electronic circuit device. The heat radiator has an extending part protruding from the electronic circuit device and extending parallel to a surface of the circuit board. A coil mounting area provided with no pattern wire is formed in a part of the circuit board facing the extending part. The flat coil element is mounted parallel to the circuit board in a state where a coil part of the flat coil element faces the coil mounting area.

Circuit board assembly and flat coil

A capacitive load driving circuit has an input terminal, a front-edge delay circuit, a back-edge delay circuit, an amplifying circuit, and an output switch device driven by the amplifying circuit. The front-edge delay circuit delays a front edge of an input signal input via the input terminal, the back-edge delay circuit delays a back edge of the input signal, and the amplifying circuit amplifies a drive control signal obtained through the front-edge delay circuit and the back-edge delay circuit.

Capacitive load driving circuit driving capacitive loads such as pixels in plasma display panels and plasma display apparatus having the capacitive load driving circuit

A plasma display apparatus includes a plurality of electrodes for electric discharge, and a drive circuit which drives the plurality of electrodes. The drive circuit includes first and second outputting circuits provided on a board, a connector provided on the board and coupled to the plurality of electrodes, and a conductive plate which is provided on the board, and provides electrical couplings between the first and second outputting circuits and the connector. The conductive plate includes a first area connected to the first outputting circuit and a second area connected to the second outputting circuit, the first area and the second area being substantially line-symmetric.

Plasma display apparatus with reduced voltage variation

A module, for mounting a driver IC constituting a drive circuit of a display apparatus using a flat display panel, is disclosed, which includes a driver IC chip for driving the display electrodes of the flat display panel and a wiring board electrically connected with the driver IC chip. A module for mounting the driver IC having this configuration comprises a first wiring unit formed with a drive power source system wiring for supplying a power source voltage, which is input to the driver IC chip, for driving the flat display panel through the driver IC chip; a second wiring unit formed with a control system wiring for supplying various signals, which are input to the driver IC chip, for controlling the driver IC chip; and a third wiring unit formed with an output terminal wiring taken out from the driver IC chip and connecting to the display electrodes of the flat display panel.

Module for mounting driver IC

A plasma-display-panel display apparatus includes a flat display panel having a plurality of address electrodes and a plurality of scanning electrodes extending transversely to the address electrodes and disposed in confronting relation to the address electrodes with a discharge space defined therebetween. A scanning electrode driver successively supplies scanning pulses to the scanning electrodes with scanning timing, and an address driver supplies address pulses according to display data to the address electrodes in synchronism with the scanning timing. The address electrodes include first and second address electrodes disposed adjacent to each other. The address pulse applied to the first address electrode rises and the address pulse applied to the second address electrode falls with a predetermined time difference therebetween.

Display apparatus with flat display panel

Disclosed is a configuration of a PDP in which different sustaining discharge signals are applied to odd-numbered ones of X electrodes and Y electrodes and even-numbered ones thereof respectively. Owing to the configuration, the wiring in a drive circuit for driving the X electrodes or Y electrodes is simplified, and a scan driver can be formed with an IC or ICs. A plasma display device has a display panel including first to third electrodes. Sustaining discharge signals that are mutually out of phase are applied alternately to adjoining ones of the first electrodes and adjoining ones of the second electrodes respectively. Consequently, first display cells are defined between the second electrodes and the first electrodes on one side of the second electrodes, and second display cells are defined between the second electrodes and the first electrodes on the other side of the second electrodes. Interlacing where the first display cells and second display cells are allowed alternately and repeatedly to glow for display is carried out. A drive circuit for driving the second electrodes includes a first drive circuit for outputting a pulsating voltage to be applied to the odd-numbered second electrodes, a second drive circuit for outputting a pulsating voltage to be applied to the even-numbered second electrodes, and third circuits associated with the second electrodes for applying the pulsating voltages, which are output from the first drive circuit and second drive circuit, to the second electrodes, and for applying a scanning signal selectively to the second electrodes. In the plasma display device, the third circuits are grouped into third odd circuits to be connected to the odd-numbered ones of the second electrodes, and third even circuits to be connected to the even-numbered ones of the second electrodes. The third odd circuits are integrated into at least one chip, and the third even circuits are integrated into at least one chip.

Plasma display device

Disclosed are a plasma display capable of preventing deterioration of display contrast deriving from priming discharge, and of minimizing a power consumption, and a driving method therefor. The plasma display comprises: a plasma display panel in which first, second, and third electrodes are arranged alternately parallel to one another on a first substrate, and fourth electrodes are arranged orthogonally to the first electrodes on the first substrate or a second substrate; a first electrode selection driver for selectively driving the first electrodes; a second electrode driver for driving the second electrodes, and a third electrode driver for driving the third electrodes. First display cells are formed at intersections between the first electrodes and second electrodes and the fourth electrodes, and second display cells are formed at intersections between the first electrodes and third electrodes and the fourth electrodes. The first display cells and second display cells are alternately and repeatedly allowed to glow for display for the purpose of achieving interlacing display. In the plasma display, during a reset period, the second electrode driver and third electrode driver apply voltages to the second and third electrodes respectively so that priming discharge can be induced in third cells. The third cells for priming are formed with the second electrodes and third electrodes.

Plasma display for high-contrast interlacing display and driving method therefor

A method of driving a plasma display panel having plural, parallel sustain and scan electrodes, corresponding to respective display lines, and plural address electrodes in opposed relationship and electrically isolated with respect to the sustain and scan electrodes and intersecting same so as to form respective discharge cells at the intersections. The method produces an interlaced display by generating discharges in selected discharge cells, in odd and even fields, between respective, different sets of the sustain and scan electrodes. Each of the odd and even fields includes a reset period in which a reset discharges are produced in the discharge cells to establish a uniform charge distribution therein, an address period in which write discharges are produced in selected discharge cells in accordance with display data and a sustain discharge period in which sustain discharge pulses are produced in the written discharge cells to establish a glow discharge, for display during the respective periods. Potential differences between the respective sets of the sustain and scan electrodes of the odd and even fields are held below a discharge initiating voltage level, thereby avoiding the otherwise occurring problem of contrast drop.

Method of driving plasma display panel, and display apparatus using the

The present invention provides a semiconductor device in which an EEPROM and an OTPROM are mounted on the same chip, a single power supply system is used, and both ROMS can be effectively used. Such a semiconductor device has the EEPROM region and the OTPROM region arranged on the same chip, and a control device which makes only the prescribed cell in either region of both regions EEPROM and OTPROM regions active.

Semiconductor device

A non-volatile semiconductor memory device comprises an EEPROM cell, a dummy cell, and a sense circuit. The EEPROM cell, the dummy cell and the sense circuit are operatively connected to a drain column line and a control column line, and the sense circuit reads out the content written in the EEPROM cell by the difference between a current flowing through the EEPROM cell from the drain column line and a current flowing through the dummy cell from the control column line. Consequently, write/erase operations of data for each one bit can be carried out in one operation, and access time can be shortened and deterioration of a cell transistor can be decreased in a read-out operation.

Growing community of inventors

Kawasaki, Japan

Haruo Koizumi