Semiconductor Technology Academic Research Center

Gunma University

Other

Sumitomo Electric Industries, Limited

Renesas Electronics Corporation

Semiconductor Components Industries, LLC

Adv Antest Corporation

Asahi Kasei Microdevices Corporation

Haruo Kobayashi

Koichiro Mashiko

Hao San

Hiroyuki Hagiwara

Atsushi Wada

Kazuya Shimizu

Hiroki Wada

Yoshiki Niki

Masato Kaneta

Tatsuji Matsuura

Akira Abe

Koji Asami

Toru Dan

Tatsuhiro Shimura

Masamichi Ishii

Hitoshi Hirata

Yasuyuki Kimura

Toshio Sugiyama

Yoshihisa Yamada

Akira Hayakawa

Ibuki Mori

Yoshitaka Jingu

Masashi Kono

Toshiro Tsukada

Tomohiko Ogawa

Yasunori Kobori

Kiichi Niitsu

Tetsuya Furuya

Naohiro Harigai

Katsuyoshi Yagi

Tomoyuki Tanabe

Kazuyuki Kobayashi

Tetsuya Taura

Masato Sakurai

Takahide Suzuki

Hiroyuki Miyajima

Satoshi Uemori

Atsushi Motozawa

Akihiro Kanbe

Masafumi Uemori

Tomonari Ichikawa

According to one embodiment, a time difference amplifier circuit includes the first amplifier including first positive and negative inputs and first positive and negative outputs, the second amplifier including second positive and negative inputs and second positive and negative outputs, first to fourth wirings, a selection circuit including the first selection element connecting the first or fourth wirings to the second positive input, and the second selection element connecting the second or third wirings to the second negative input, and a control circuit connecting the amplifiers by the first and second wirings or by the third and fourth wirings.

Time difference amplifier circuit

According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.

Multi-bit delta-sigma time digitizer circuit and calibration method thereof

An envelope tracking power supply circuit is a power supply circuit for generating an output voltage according to the envelope of a high frequency signal and includes a voltage follower circuit for receiving an envelope signal and outputting a voltage according to the envelope signal; two parallel resistors connected in parallel between the output of the voltage follower circuit and an output terminal; hysteresis comparators for detecting respective voltage drops in the parallel resistors and generating voltages according to the voltage drops; and switching converters for performing switching according to the respective voltages outputted from the hysteresis comparators and outputting a voltage to the output terminal.

Envelope tracking power supply circuit and high-frequency amplifier including envelope tracking power supply circuit

In an ADPLL circuit, on the basis of a gain of a digitally controlled oscillator estimated when a loop gain of a certain value is set in the loop filter and on the basis of a device parameter of the digitally controlled oscillator, the DCO gain estimation unit estimates a gain of the digitally controlled oscillator when a loop gain of another value is set in the loop filter.

PLL circuit, and radio communication apparatus equipped with same

To provide a complex bandpass &#x394;&#x3a3;AD modulator capable of suppressing the influence of an image component caused by a mismatch between I- and Q-channels on a signal component with low power consumption. A complex bandpass &#x394;&#x3a3;AD modulatoris configured by a subtraction unit, a complex bandpass filter, an addition unit, a noise extraction circuit unit, an ADC unit, and a DAC unit. The noise extraction circuit unitextracts a quantized noise signal of the ADC unitbased on an input signal of the ADC unitand an output signal of the DAC unit, delays the extracted quantized noise signal by one sample time, phase-rotates the delayed signal by a predetermined angle, and feeds back the rotated signal to the input side of the ADC unit. Thus, a complex bandpass &#x394;&#x3a3;AD modulator capable of suppressing the influence of the image component caused by a mismatch between I- and Q-channels on the signal component with low power consumption is provided.

Complex bandpass &#x394;&#x3a3;AD modulator and digital radio receiver

The invention provides a technique to widely spread the frequency spectrum of switching noise generated by a switching action and to reduce the noise level at a particular frequency. A switching regulator (A) includes a computing unit with computing function. First, in the computing unit, a pulse-width-modulation processing unit (PWM) () performs pulse-width-modulation processing of receiving a feedback signal corresponding to the output of a detectorto determine an on-duty cycle of a pulse signal. Subsequently, for the signal and data obtained by the PWM () to be subjected to further modulation processing for spectrum spreading, a branching processing is performed by making changing-over unit () randomly select asynchronous-modulation processing unit (ASM) () or pulse-position-modulation processing unit (PPM). When the PPM is selected, another branching processing is performed by making the changing-over unit () select a first PPM () or a second PPM () depending on the on-duty cycle.

Switching regulator

An SAR ADC includes a digital-to-analog converter, a first comparator that compares an input analog signal with a reference analog signal, a second comparator that compares an input analog signal with a reference analog signal, a selection circuit that selects one of comparison results of the first comparator and the second comparator, and a control circuit that changes the multibit digital signal sequentially based on the selected comparison result in a plurality of steps so that the reference analog signal becomes closer to the input analog signal, and the control circuit controls the selection circuit to select the comparison result of the first comparator up to an intermediate step on the way of the plurality of steps and to select the comparison result of the second comparator after the intermediate step, and changes the bit value of the multibit digital signal according to the non-binary algorithm.

Analog-to-digital converter

A conventional DC/DC converter with both a step-up function and a step-down function has a drawback that its output voltage will be discontinuous when its operations are switched. An error signal, which is representative of a difference between a target voltage and a present voltage, is inputted to both a step-down switching control circuit and a step-up switching control circuit. When the difference between the target voltage and the present voltage is below a predetermined value, the switching of the step-down and step-up converters by the step-down and step-up switching control circuits, respectively, are caused to concurrently run in a time division manner.

DC/DC converter

A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a difference between the first delay amount and the second delay amount is smaller than the first delay amount and the second delay amount.

Time-to-digital converter

Provided is an AD converting apparatus that converts an analog input signal into a digital output signal, comprising a plurality of AD converters supplied with sampling clocks differing from each other by prescribed phase amounts, each AD converter outputting an individual signal obtained by digitizing the input signal according to the supplied sampling clock; a plurality of amplitude-dependent characteristic correcting sections that are provided to correspond to the plurality of AD converters, each amplitude-dependent characteristic correcting section generating a corrected individual signal by correcting the individual signal output by the corresponding AD converter using a correction factor corresponding to an amplitude of the individual signal; and a combining section that generates the output signal by combining a plurality of the corrected individual signals.

Analog digital convert apparatus, analog digital convert method, control apparatus and program

An AD converter that operates at high speed and precision of which is disclosed. The AD converter includes an analog-to-digital (AD) conversion part that samples an analog signal according to a sampling clock and converts it into a digital signal, a jitter measuring circuit that measures the jitter of the sampling clock, and a correction circuit that corrects a digital signal output from the AD conversion part. The AD converter further comprises a clock source and a sampling generating circuit that generates a sampling clock by dividing the clock generated by the clock source, wherein the jitter measuring circuit measures the jitter of the sampling clock with respect to the click on the basis of a clock CK.

Analog-to-digital (AD) converter and analog-to-digital conversion method

A high-precision &#x394;&#x3a3; modulator reduces nonlinear noise due to the use of a multibit DAC and has little hardware and power consumption. A digital signal is DA converted and fed back to a subtraction circuit supplied with an analog signal. The DAC used in this feedback circuit uses a DAC (DWADAC) that includes a weighted pointer so that input digital signals are supplied in order to a plurality of segment elements that construct the DAC. In this DWADAC, the construction and number of the pointer is set based on the type and order of the filter disposed before the ADC.

High-precision multi-band pass &#x394;&#x3a3; modulator

A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area.

Current mirror circuit

There is disclosed a current mirror circuit comprising a first transistor having a first electrode connected to a first potential, a second electrode connected to a second potential lower than the first potential, and a third electrode connected to a third potential higher than the second potential, a second transistor having a first electrode connected to the first potential and the first electrode of the first transistor, and a second electrode connected to the second potential, an operational amplifier having a high-potential input connected to the third potential and the third electrode of the first transistor, and a low-potential input connected to the third electrode of the second transistor, and a third transistor having a first electrode connected to an output of the operational amplifier, a second electrode connected to the low-potential input and the third electrode of the second transistor, and a third electrode used as an output terminal.

A continuous-time band-pass &#x394;&#x3a3; AD modulator subtracts an analog signal from a DA converter from an inputted analog signal, outputs an analog signal having a subtraction result to an AD converter via a continuous-time analog band-pass filter, outputs a digital signal from the AD converter to the DA converter, and outputs the same digital signal as a digital signal subjected to a band-pass &#x394;&#x3a3; AD modulation processing. The highest input frequency 'fin' of the inputted analog signal is substantially set to three-fourths of a sampling frequency 'fs'. The DA converter is configured to convert the inputted digital signal into the analog signal, and outputs the analog signal, which is inverted or not in response to a value of the inputted digital signal and has an amplitude of substantially zero and a gradient of substantially zero at a timing k/(2fs).

Band-pass &#x394;-&#x3a3; AD modulator for AD-converting high frequency narrow-band signal with higher precision and lower power consumption

Growing community of inventors

Kiryu, Japan

Haruo Kobayashi