Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Haruo Keida

Takashi Tsukamoto

Nobutaka Nagasaki

Yasushi Akao

Shinkichi Hotta

Kunihiko Nakada

Hajime Yasuda

Yoshiyuki Miwa

Tsuyoshi Jouno

Keiichi Kurakazu

Hiroto Kawagoe

Kazuyoshi Kikuta

An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provided which is capable of supplying selectively a signal, input to the internal bus, to a specified functional module in place of an individual signal.

Semiconductor integrated circuit device with test mode for testing CPU

An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

Data processor in which external sync signal may be selectively inhibited

In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.

Data processor

A single-chip microcomputer has external terminals outputting a system clock signal, an address signal, and a data signals. External equipment such as an external memory is operated by address and signal which are output when the system clock signal changes. In the single-chip microcomputer of this invention, the operation of an address signal output circuit and that of a data signal output circuit are controlled by a signal output from a digital delay circuit which receives the system clock signal. According to this circuit construction, the hold time between the change in the system clock and the change in the address and data signals is determined by the delay circuit which exhibits a digital operation, so that the hold time can be set accurately without being affected adversely by any variation in the circuit elements due to the manufacturing process, or by temperature changes.

Microcomputer with synchronized data transfer

A switching circuit for use as, e.g., a digitron driver circuit in an electronic desk top calculator, comprises a driving MISFET whose source terminal is connected to a ground reference potential, at least one protective MISFET whose source terminal is connected to a drain terminal of the driving MISFET, and a bias power source which is connected through a load to a drain terminal of the protective MISFET. A d.c. voltage is applied to a gate terminal of the protective MISFET and an output signal is derived from the drain terminal of the protective MISFET on the basis of an input signal which is supplied to a gate terminal of the driving MISFET. The driving MISFET is an enhancement mode transistor, while the protective MISFET is a depletion mode transistor, whereby the withstand voltage of the switching circuit is enhanced.

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Tokorozawa, Japan

Haruo Keida