Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Haruo Ii

Hiroyuki Uchiyama

Ryoichi Hori

Yasushi Takahashi

Kazuyuki Miyazawa

Hisashi Nakamura

Masamichi Ishihara

Hidetoshi Iwai

Masaya Muranaka

Satoshi Oguchi

Hiromi Matsuura

Yoshihisa Koyama

Hidetomo Aoyagi

Shigetoshi Sakomura

Takeshi Kizaki

Toshitugu Takekuma

Toshitsugu Takekuma

Kazuya Ito

Toshitugu Takemuma

A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Semiconductor memory device with improved substrate arrangement to

When the data of a mask pattern of a phase shift mask is to be made, the pattern data is separated into a real pattern data layer having the data of real patterns and a phase shift pattern data layer having the data of phase shift patterns. After this, it is verified whether or not the mask pattern satisfies the regulation of the gap of in-phase patterns, in which lights having transmitted through patterns adjacent to each other are in phase. It is also verified whether or not the mask pattern satisfies the regulation of the gap of out-of-phase patterns, in which lights having transmitted through patterns adjacent to each other are out of phase.

Process for fabricating phase shift mask and process of semiconductor

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Akishima, Japan

Haruo Ii