Qlogic Corporation

Occam Networks

Accelerated Networks

Harun Muliadi

Rexford Alan Hill

William Clinton Terrell

Jean Kodama

Tracy Edmonds

Stephen How

Michael Nishimura

Wayland Joeng

Eric Russell Peterson

Norman Chan

John Neil Jensen

Vardan Antonyan

Alfred Abkarian

Kiran Munj

A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction. The nonvirtual transaction accomplishes the intent of the virtual transaction but operates on an actual network port, for example, a storage device.

Router with routing processors and methods for virtualization

Router and methods for distributed virtualization

Router and methods using network addresses for virtualization

A system of expanding addressing in an addressing constrained environment. A bus that defines a limited number of addresses couples together a master and a plurality of slaves. When each slave has multiple possible target ports, a maximum granularity provided by the addressing may be exceeded. By using a portion of a transmission header as an internal address, the maximum addressing may be expanded to greater granularity. The internal address is then translated in the slave to recover the external address in the header.

Expanded addressing for traffic queues and prioritization

A method and apparatus for synchronizing ATM cells is disclosed. A synchronization unit receives a data clock signal and a plurality of control signals. Based on those signals, a sync pulse is generated. If synchronization is not achieved within a predetermined time period, the sync pulse is shifted one bit location. Through iterative shifting of the sync pulse, synchronization is ultimately achieved.

Method and apparatus to perform cell synchronization in an asynchronous transfer mode network

A system and method of decoupling timing in a high speed bus system. A master/slave translator is coupled between a master device and a slave device. A pseudo slave of the master/slave translator responds to the master in a first timing protocol. A pseudo master of the master/slave translator masters the slave devices under a different timing protocol. The master/slave translator causes the master to believe its communications with the slave device are occurring under the first protocol.

Pseudo master/slave decoupling of high speed bus communications timing

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Thousand Oaks, CA, United States of America

Harun Muliadi