Toshiba Memory Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Harumi Seki

Masumi Saitoh

Takayuki Ishikawa

Shosuke Fujii

Kensuke Ota

Yuichiro Mitani

Takuya Hirohashi

Hidenori Miyagawa

Takamitsu Ishihara

Yusuke Higashi

Yuya Matsubara

Reika Tanaka

Kazunori Harada

Hiromichi Kuriyama

Masato Koyama

Masamichi Suzuki

A semiconductor memory device according to an embodiment includes a stacked body in which a gate electrode layer and a first insulating layer are alternately stacked in a first direction, a semiconductor layer in the stacked body and extending in the first direction, a second insulating layer between the semiconductor layer and the stacked body, a third insulating layer provided between the second insulating layer and the stacked body, and a first layer between the second insulating layer and the third insulating layer. The first layer contains silicon and nitrogen and includes a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region contains or does not contain fluorine, the second region contains fluorine, and a fluorine concentration of the second region is higher than a fluorine concentration of the first region.

Semiconductor memory device

A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a first insulating layer between the semiconductor layer and the first gate electrode layer; a second insulating layer between the first insulating layer and the first gate electrode layer, the second insulating layer having a first portion containing a ferroelectric material; and a first layer between the first insulating layer and the second insulating layer, the first layer containing silicon, nitrogen, and fluorine, the first layer having a first region and a second region between the first region and the second insulating layer, the first layer having a second atomic ratio of nitrogen to silicon in the second region higher than a first atomic ratio of nitrogen to silicon in the first region, and the first layer having fluorine concentration higher than the second region.

A semiconductor memory device of an embodiment includes a first gate electrode layer and a second gate electrode layer extending parallel to each other, a semiconductor layer between the first and the second gate electrode layer intersecting with the first and the second gate electrodes, and a dielectric layer surrounding the semiconductor layer, the dielectric layer containing oxygen and one of hafnium oxide or zirconium, the dielectric layer including a first region containing crystal of orthorhombic or trigonal as a main component between the first gate electrode layer and the semiconductor layer, a second region containing crystal of orthorhombic or trigonal as a main component between the second gate electrode layer and the semiconductor layer, and a third region containing a substance other than crystal of orthorhombic or trigonal as a main component between the first region and the second region.

Semiconductor memory device having ferroelectric field effect transistor

A semiconductor memory device according to an embodiment includes: a semiconductor layer; a gate electrode layer; a first insulating layer provided between the semiconductor layer and the gate electrode layer, the first insulating layer containing silicon (Si), nitrogen (N), and fluorine (F), and the first insulating layer including a first region; a second insulating layer provided between the first insulating layer and the gate electrode layer; and a charge storage layer provided between the first insulating layer and the second insulating layer, the charge storage layer containing silicon (Si) and nitrogen (N), and the charge storage layer including a second region, in which a second atomic ratio (N/Si) in the second region is larger than a first atomic ratio (N/Si) in the first region, and in which a first fluorine concentration in the first region is higher than a second fluorine concentration in the second region.

Semiconductor memory device and method of manufacturing semiconductor memory device

According to one embodiment, a semiconductor memory device includes: a first interconnect layer; a second interconnect layer adjacent to the first interconnect layer; a semiconductor layer between the first and second interconnect layers; a first charge storage layer between the first interconnect layer and the semiconductor layer; and a second charge storage layer between the second interconnect layer and the semiconductor layer. A first distance between the first and second interconnect layers is shorter than a second distance between the first and second charge storage layers.

According to one embodiment, a memory device includes a first interconnect, a second interconnect, a first layer, a second layer. The first interconnect includes a first region and a second region. The first region extends in a first direction and includes a first metallic element. The second region extends in the first direction and includes the first metallic element and nitrogen. The second interconnect extends in a second direction crossing the first direction. A portion of the second region is positioned between the second interconnect and a portion of the first region. The first layer is provided between the second interconnect and the portion of the second region. The second layer is provided between the first layer and the second interconnect. The second layer includes at least one of silicon or a second oxide. The silicon is monocrystalline, polycrystalline, or amorphous.

Memory device with multiple interconnect lines

According to one embodiment, a variable resistance element includes first and second conductive layers and a first layer. The first conductive layer includes at least one of silver, copper, zinc, titanium, vanadium, chrome, manganese, iron, cobalt, nickel, tellurium, or bismuth. The second conductive layer includes at least one of platinum, gold, iridium, tungsten, palladium, rhodium, titanium nitride, or silicon. The first layer includes oxygen and silicon and is provided between the first conductive layer and the second conductive layer. The first layer includes a plurality of holes. The holes are smaller than a thickness of the first layer along a first direction. The first direction is from the second conductive layer toward the first conductive layer. The first layer does not include carbon, or a composition ratio of carbon included in the first layer to silicon included in the first layer is less than 0.1.

Variable resistance element and memory device

According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.

Memory device

According to one embodiment, a nonvolatile memory device includes a first conductive layer, a second conductive layer, and an intermediate layer. The first conductive layer includes a first element. The first element includes a at least one selected from the group consisting of Ag, Cu, Ni, Co, Ti, Al, and Au. The intermediate layer is provided between the first conductive layer and the second conductive layer. The intermediate layer includes an oxide. The oxide includes a second element and a third element. The second element includes at least one second element being selected from the group consisting of Ti, Ta, Hf, W, Mg, Al, and Zr. The third element is different from the second element and includes at least one selected from the group consisting of Si, Ge, Hf, Al, Ta, W, Zr, Ti, and Mg.

Nonvolatile memory device

According to one embodiment, a memory device includes a first layer, a second layers, a third layer provided between the first layer and the second layer, and first electrodes. The first layer includes first interconnections and a first insulating portion provided between the first interconnections. The second layer includes second interconnections and a second insulating portion provided between the second interconnections. The third layer includes first and second portions including silicon oxide. The first portion is provided between the first and the second interconnections. The second portion is provided between the first and the second insulating portions. The first electrodes are provided between the first interconnections and the first portion, and include a first material. The second interconnections include a second material. The first material is easier to ionize than the second material. A density of the first portion is lower than a density of the second portion.

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Kawasaki, Japan

Harumi Seki