Victor Company of Japan, Limited

Hitachi, Ltd.

Nippon Victor Kabushiki Kaisha

Harukuni Kobari

Takayuki Sugahara

Toshio Kuroiwa

Chitoshi Hibino

Yasuhiro Yamada

Norihiko Fuchigami

Susumu Suzuki

Junzo Suzuki

Hiroyuki Saito

Takao Arai

Takashi Hoshino

Takashi Takeuchi

Masaharu Kobayashi

Shigeru Yamazaki

Masatsugu Kitamura

Kaoru Kobayashi

Hirotoshi Ohno

Hiroyoshi Yoshikawa

Kohbun Sakagami

Nobuchika Ochi

An audio signal is compressively encoded into encoding-resultant audio data. A video signal is compressively encoded into encoding-resultant video data. An audio time stamp for audio-vide synchronous reproduction is added to every unit of the encoding-resultant audio data. A video time stamp for audio-video synchronous reproduction is added to every unit of the encoding-resultant video data. The time-stamp-added audio data and the time-stamp-added video data are multiplexed into main data. To a plurality of first after-recording-purpose data for at least one of (1) the encoding-resultant audio data and (2) the encoding-resultant video data which form the main data, time stamps for reproduction synchronous with a portion of the main data and identification information for identifying the plurality of first after-recording-purpose data are added to convert the first after-recording-purpose data into second after-recording-purpose data. The second after-recording-purpose data are made into bit streams without being multiplexed with the main data.

After-recording apparatus

When a code word sequence is generated by converting input data words of p bits into code words of q bits and concatenating adjacent ones of the code words with a merge bit sequence of r bits in order to obtain the best DSV value, according to one aspect, the adjacent code words are concatenated with the merge bit sequence of r bits which is selected, free from the restriction of the minimum run-length of (d+1)T and the maximum run-length of (k+1)T based on the run-length limiting rule RLL(d, k) but permitting the minimum run-length of (d+1)T and the maximum run-length of (k+2)T. According to another aspect, a merge bit sequence to be inserted after a current code word is selected by prefetching the current code word, a next code word, and a further next code word, temporarily concatenating these code words with merge bit sequences of r bits respectively to prepare code word sequence candidates free from the predetermined run-length limiting rule, calculating the DSV values of the code word sequence candidates, selecting one of the code word sequence candidates having a DSV value whose absolute value is closest to zero, and selecting the merge bit sequence between the current code word and the next code word of the selected merge bit sequence candidate. According to a further aspect, the input data words are encoded by a p-q modulation scheme after introducing for a predetermined period, as an input data word, specific data comprising alternating current signals or direct current signals which would cause a modulation device that prefetches only the next code word to output a code word sequence which includes particular frequency components.

Modulation device, modulation method and recording medium

Among a first and second video data each being variable length coded data such that an occupancy of a decoder buffer is neither overflown nor underflown, having an end code at a rear end thereof and being comprised of a plurality of compressed portion data, a value related to a buffer occupancy at a decoding timing of the last picture of the first video data is compared by an invalid data amount calculator 13 with the buffer occupancy at the decoding timing of the first picture of the second video data. According to a data amount corresponding to a difference between the occupancies when the result of comparison is a predetermined one, the invalid data of this data amount is added by an invalid data adder 14 to the last picture of the first video data and the second video data is connected by a video data connector 15 to the first video data.

Variable length coded data processing method and device for performing

A circuit arrangement comprises a frequency response control circuit for controlling the level around a particular frequency of an input PCM signal in accordance with a control signal which is produced as a function of the difference between levels of positive peaks and/or negative peak corresponding to a logic bit pattern 1010 of a data synchronous signal of the PCM signal having a predetermined format. The level detection may be performed by a plurality of sample-and-hold circuits, and the difference is obtained by way of an adder-subtractor. The circuit may be arranged to constitute either a feedback loop in which level detection is effected by using a frequency response controlled PCM signal, or a feedforward system in which level detection is effected by using the input PCM signal whose frequency response has not been controlled. An output signal from the frequency response control circuit is then applied to two comparators of a conventional data acquisition circuit.

Circuit arrangement for a data acquisition circuit of a PCM processor

A random access memory has: upper and lower address limits, an address input responsive to an address counter, a write enable input, a read enable input, a data input bus, and data output bus. The address counter is supplied with a synchronization signal having a frequency determined by the frequency of a variable frequency data source. A signal having first, second and third values, respectively indicative of the address input of the memory being at the upper limit for the memory address, the lower limit for the memory address and between the upper and lower limits, is derived in response to the count in the address counter. First, second and third oscillators respectively derive first, second and third fixed frequencies such that the third frequency is greater than the second frequency and the second frequency is greater than the first frequency. The first, second and third fixed frequencies are coupled to the address counter while the signal has the third, second and first values.

Memory control circuit for removing jitter

A Reed-Solomon code generator applicable to a digital signal recording/playback apparatus checks or corrects code errors in digital signals. The code generator eliminates the need for costly read only memory devices (ROM tables) and uses inexpensive registers, modulo 2 adders and multipliers instead.

Reed-Solomon code generator

A system for defeating erroneous correction in a digital signal reproducing apparatus. The system includes a reproducing circuit for reproducing a signal sequence in which information words and error correcting words are interleaved. A memory stores the reproduced digital signal sequence and produces a digital signal sequence made up of the information words and error correcting words, which are then de-interleaved and arranged in an original sequence. A correcting circuit corrects adjacent errors with respect to the digital signal sequence produced from the memory. A digital-to-analog converter converts a digital information signal obtained from the correcting circuit into an original analog information signal. The correcting circuit calculates partial syndromes according to predetermined equations and detects the number of erroneous words in one block which is made up of interleaved words. The error correcting operation is stopped when there are certain set of conditions which are related to the values of the partial syndromes and when the number of erroneous words are satisfied. The system continues to stop the correcting operation until other sets of conditions are satisfied, in order to correct errors of up to two words in each of the blocks made up of the de-interleaved words.

System for defeating erroneous correction in a digital signal

A circuit for protecting a horizontal synchronous signal comprises a horizontal synchronous signal detecting circuit responsive to horizontal synchronous pulses included in a composite synchronous signal of a reproduced PCM signal, first and second horizontal synchronous pulse supplementing or adding circuits and an output switching circuit. The output switching circuit operates so that the first supplementing circuit delivers a first supplementary pulse in the absence of a single pulse of the original horizontal synchronous signal, and the second supplementing circuit produces one or more second supplementary pulses in the absence of a plurality of continuous pulses of the original horizontal synchronous signal. When the circuit returns to a condition in which produced horizontal synchronous pulses are synchronous with the original horizontal synchronous pulses, the time interval between adjacent pulses of the original pulses is detected to see whether the interval is either longer or shorter than a predetermined value. As a result, when a pulse first appeared after the returning point is within the predetermined interval, that pulse is removed so that the number of output horizontal synchronous pulses is correct.

Circuit and method for protecting a horizontal synchronous signal

A double error correcting system is used in a digital signal reproducing apparatus, which is capable of correcting errors in two information vectors (information words) among a plurality of information vectors within one block by use of elements in a small number of correcting matrices and by using a memory device having a small memory capacity. A register is not required for temporarily storing the operational result obtained half-way between a plurality of performed operations. Instead, corrected information vectors are obtained from a memory circuit.

Double error correcting system in digital signal reproducing apparatus

An error correcting circuit particularly for an audio equipment makes use of the so-called adjacent code correction technology and an error pointer generated by the error detection code (CRCC). The circuit comprises a counter starting to count clock pulses in response to an operation start signal, a timing signal generator for steps of correction operation, a correction operation circuit operative with the timing signal, a storage circuit for storing operation results of the correction operation circuit, a monitoring circuit for monitoring the degree of execution of the correction operation steps in the correction operation circuit, using the output of the counter and a control circuit for controlling the storage of the operation results in the storage circuit, depending upon the output of the monitoring circuit.

Circuit for correcting error in digital information signal

A memory control system comprises a first memory supplied with an incoming modulated digital signal which is formed by subjecting an analog signal to digital signal processing of discontinuous level modulation system, and a first control circuit for supplying a control signal to the first memory. The first control circuit producing the control signal for controlling the first memory in such a manner that the total memory capacity of the first memory is partitioned into a plurality (k) of memory capacity segments having given capacity values (lengths) for use, and the modulated digital signal is written in and further the modulated digital signal thus written in is read out with the order thereof rearranged, interrelatedly with the circulation of addresses through the plurality of divided memory capacity segments while maintaining constant the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments.

Memory control system

A system for time compression and expansion of audio signals comprises a filter for filtering the fundamental frequency component of an input signal reproduced at a speed differing from that at the time of recording, first and second memory devices for carrying out writing in or memorizing and reading out at speeds in accordance with the frequency of applied clock pulses, a control signal forming circuit for forming gate control signals and clock pulse signals of different frequency from the output fundamental frequency component of the filter in synchronism with the pitch period thereof, and gates controlled by the gate control signals to pass or not pass the output signals of the first and second memory devices. A time compressed or expanded signal synchronized with the pitch period of the fundamental frequency component of the input signal is led out through these gates.

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Yokohama, Japan

Harukuni Kobari