Kabushiki Kaisha Toshiba

Other

Haruki Toda

Hitoshi Kuyama

Shozo Saito

Kaoru Tokushige

Kenji Tsuchida

Koichi Kubo

Shigeo Ohshima

Hiroshi Sahara

Toshiaki Edahiro

Koichi Magome

Yukihito Oowaki

Katsuaki Isobe

Tsuneaki Fuse

Hironobu Akita

Hiroyuki Koinuma

Masahiro Kamoshida

Tatsuo Ikawa

Toshihiro Suzuki

Satoshi Eto

Hiroto Nakai

Hirofumi Inoue

Yuji Watanabe

Masaharu Wada

Nobuo Watanabe

Kenji Komatsu

Hiroyuki Nagashima

Kenichi Murooka

Kuninori Kawabata

Yuichiro Mitani

Satoru Takase

Jun Deguchi

Yuui Shimizu

Mitsugi Ogura

Katsumi Abe

Fumihiro Kohno

Yusuke Higashi

Naokazu Miyawaki

Shuichi Toriyama

Masakazu Kiryu

Kiminobu Suzuki

Shigeo Oshima

Akiko Nara

A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store a code composed of symbols expressed by elements in a finite field Zp (p is a prime), wherein a set of two cells is defined as a pair cell and a combination of physical quantity levels of the two cells contained in the pair cell is defined as a pair cell level, wherein the pair cell uses a pair cell level of plural pair cell levels, which maximizes or minimizes a physical quantity level of one cell contained in the pair cell, to assign elements in the Zp to the pair cell levels, thereby storing symbols of the code.

Memory system

A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.

Semiconductor memory device

A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2&#x3c;p&#x3c;2), and a mapping unit operative to execute mapping of the target data from the data processing unit as page data within the page buffer.

Memory system and memory controller

A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state.

Semiconductor memory device executing a write operation with first and second voltage applications

A memory system according to the embodiment comprises a cell array of unit cell arrays each including memory cells; and an access circuit, wherein the memory cell changes from a first resistance state to a second resistance state on application of a first polarity voltage, and changes from the second resistance state to the first resistance state on application of a second polarity voltage, the access circuit provides the first and second lines connected to an access-targeted memory cell with access potentials, and brings at least one of the first and second lines connected to an access-untargeted memory cell into a floating state to make access to the access-targeted memory cell, the unit cell array includes first spare lines to provide redundancy for the first lines, and an alignment of the first lines includes a certain number of the first spare lines arranged in a certain cycle.

Variable resistance memory system with redundancy lines and shielded bit lines

A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different physical states; and an access circuit operative to make access to the memory cell via the first line and the second line, wherein the access circuit, on writing data in the access cell, uses a non-access-side first line driver to electrically connect a non-access first line adjacent to an access first line to a first potential power supply via a diode-connected transistor.

A semiconductor memory device according to the embodiment comprises memory cells each having asymmetrical voltage-current characteristics, wherein the memory cell has a first state, and a second state and a third state of higher resistances than that in the first state, wherein the memory cell, (1) in the second state, makes a transition to the first state on application of a first voltage of the first polarity, (2) in the first state, makes a transition to the second state on application of a second voltage of the second polarity, (3) in the first state, makes a transition to the third state on application of a third voltage of the second polarity (the third voltage&#x3c;the second voltage), and (4) in the third state, makes a transition to the first state on application of a fourth voltage of the first polarity (the fourth voltage&#x3c;the first voltage).

A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different resistance states; and an access circuit operative to execute a write sequence of changing the resistance state for writing data in the memory cell, wherein the access circuit, on the write sequence, executes a first step of changing all memory cells provided at the intersections of access first lines and the access and fault second lines to the high resistance state, and a second step of changing all or part of access cells connected to the access second line to the low resistance state.

A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively.

Resistance change memory device that stores a reversible resistance value as data

A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly.

According to one embodiment, a semiconductor memory device includes a memory cell array including blocks, each block being capable of executing a write, read, or erase operation independently of other blocks. A control portion is configured to execute the operation of a first block among the blocks in a first cycle, set a selection inhibited region within a range of a predetermined distance from the first block, until a temperature relaxation time for relaxing a temperature of the first block has elapsed, set a region except the selection inhibited region among the blocks as a second block, and execute the operation of the second block in a second cycle.

Semiconductor memory device and method of controlling the same

A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array.

Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array

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Yokohama, Japan

Haruki Toda