Renesas Electronics Corporation

Hitachi, Ltd.

Renesas Technology Corp.

Bayer Healthcare Aktiengesellschaft

Haruka Shimizu

Natsuki Yokoyama

Koichi Arai

Yasuaki Kagotoshi

Nobuo Machida

Karl-Heinz Schlemmer

Frank Wunder

Joachim Schuhmacher

Peter Kolkhof

Lars Bärfacker

Katsumi Ishikawa

Walter Hübsch

Hanna Tinel

Yuki Mori

Junichi Sakano

Raimund Kast

Masahiro Nagasu

Eva-Maria Becker

Johannes Köbberling

Hidekatsu Onose

Gunter Karig

Naoki Tega

Michael Härter

Mieko Matsumura

Klaus Münter

Norifumi Kameshiro

Keisuke Kobayashi

Arnel B Concepcion

Dai Tsugawa

Jens Ergüden

Susanne Zuleger

To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n-type source region.

Semiconductor device and power conversion device

In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Normally-off power JFET and manufacturing method thereof

A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n-type source layer on a surface of an n-type drift layer formed on an n-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n-type drift layer with a silicon oxide film formed on the n-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Semiconductor device with counter doped layer

A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.

Electronic circuit device

Manufacturing method of semiconductor device and semiconductor device

Power JFET

On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n-type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.

Semiconductor device

The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an ntype layer on a surface of the trench. In this manner, the pn junction region corresponding to the junction region between a ptype gate region and an ntype source region is exposed on a main surface of a semiconductor substrate instead of on the damaged sidewall of the trench, and also the exposed region thereof is narrowed. Accordingly, the leakage current in the pn junction region can be reduced.

Semiconductor device and manufacturing method of the same

There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.

Semiconductor device with large blocking voltage and manufacturing method thereof

In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.

Semiconductor device including normally-off type junction transistor and method of manufacturing the same

A junction FET having a large gate noise margin is provided. The junction FET comprises an nlayer forming a drift region of the junction FET formed over a main surface of an nsubstrate made of silicon carbide, a player forming a gate region formed in contact with the nlayer forming the drift region and a gate electrode provided in an upper layer of the nsubstrate. The junction FET further incorporates pn diodes formed over the main surface of the nsubstrate and electrically connecting the player forming the gate region and the gate electrode.

Semiconductor device with large blocking voltage

An object of the present invention is to reduce the conducting loss of an existing conversion circuit while suppressing its noise. The present invention is typically a circuit arrangement includes at least one switching device and a free-wheel diode connected in parallel with the switching device. The free-wheel diode is formed by connecting a silicon PiN diode in parallel with a Schottky barrier diode that uses a semiconductor material having a wider band gap than silicon as a base material. The silicon PiN diode and Schottky barrier diode are separate chips.

Circuit arrangement having a free-wheel diode

Growing community of inventors

Kodaira, Japan

Haruka Shimizu