Kioxia Corporation

Haruka Mori

Mitsunori Tadokoro

Hajime Yamazaki

Akinori Nagaoka

Akihiro Nagatani

Shinji Yonezawa

Konosuke Watanabe

Yukie Kumagai

Mitsusato Hara

Eiji Sukigara

A memory system includes a memory controller and a first number of memory elements connected to the memory controller via one or more channels. The memory controller includes a second number of polling circuits and a first processor. Each polling circuit receives designation of one memory element out of the first number of memory elements and executes a polling operation. The polling operation is an operation to repeat an inquiry to the designated memory element until detecting that a status of the designated memory element is a ready status. The first processor selects a polling circuit that is not executing the polling operation among the second number of polling circuits. The first processor designates, for the selected polling circuit, one memory element out of the first number of memory elements and causes the selected polling circuit to execute the polling operation on the designated one memory element.

Memory system and control method

According to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller. The controller manages whether each of the nonvolatile memory chips is in a busy state or not. When one or more requests issued by a host are stored in at least one queue of the host, the controller identifies, from the one or more requests, a first request for a first nonvolatile memory chip that is not in the busy state. The controller executes a process in accordance with the identified first request.

Memory system and method of controlling memory chips

According to one embodiment, a controller for a memory system including a nonvolatile memory with physical blocks sets logical blocks including the physical blocks, manages a first table having a first value indicating a threshold voltage to be used for reading data from each logical block, a second table for each physical block having a corrected threshold voltage that has been statistically determined to be an outlier in association with a second value indicating the corrected threshold voltage for the physical block. The controller performs a threshold voltage tracking for identifying a threshold voltage suitable for reading data from a physical block if a reading fails, and then retries the reading using the threshold voltage obtained by the threshold voltage tracking. The controller updates the first table if the physical block is not listed in the second table, but not otherwise.

Memory system and method for controlling the same

A memory system includes a plurality of memory chips, a memory, and a controller. The memory chips are capable of operating in parallel. The memory includes a physical channel region and a plurality of virtual channel regions, each corresponding to one of a plurality of processes executed on the memory chips according to the requests. The controller stores the requests issued from the host in the physical channel region in order of acquisition from the host, and an entry for each of the requests in one of the virtual channel regions. When a required degree of parallelism of the processes is less than a threshold, the controller selects a next request to be executed using the physical channel region. When the required degree of parallelism is greater than or equal to the threshold, the controller selects a next request to be executed using one of the virtual channel regions.

Memory system

A memory system includes a non-volatile memory including first and second memory chips connected to a channel, each chip outputting a first signal indicating whether the chip is in a busy state, a first queue storing commands to be executed by the first chip, a second queue storing commands to be executed by the second chip, a processor configured to issue a second signal indicating whether a command in the first or second queue is a first-type or a second-type command, the first-type command causing the first or second chip to be in the busy state longer than the second-type command, a first arbiter selecting from the first and second queues a command to be executed next based on the first and second signals, and an interface controller sending the selected command via the channel to the first or second memory chip.

Memory system and command determination method

A memory system includes a memory controller and a first memory. The memory controller writes a plurality of first data segments of user data and metadata to a plurality of first segment regions of the first memory according to a first order. In response to a read request from a host, the memory controller individually identifies a plurality of second segment regions to which a plurality of second data segments corresponding to requested user data has been written. The memory controller determines whether or not to perform a prefetch operation according to a second order and a third order. The second order is an order of reading the second data segments from the second segment regions. The third order corresponds to the first order excluding the order of write destinations of the metadata.

Memory system and method

According to one embodiment, a controller executes a first operation. The first operation includes reading a plurality of data units from a nonvolatile memory and executing a process on the read plurality of data units. The process includes an inverse conversion of a conversion applied to the plurality of data units and first decoding using the plurality of data units that has executed the inverse conversion. The controller acquires first information from one of the plurality of data units that has executed the first operation. The controller compares the acquired first information with an expected value of the first information and re-executes the first operation when the acquired first information and the expected value are not equal to each other.

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Fujisawa, Japan

Haruka Mori