Hitachi, Ltd.

Micron Technology Incorporated

Hitachi Device Engineering Co., Ltd.

Hitachi Denshi Kabushiki Kaisha

Haruhisa Ando

Shinya Ohba

Iwao Takemoto

Masaaki Nakai

Toshifumi Ozaki

Masakazu Aoki

Masaharu Kubo

Norio Koike

Toshiyuki Akiyama

Takuya Imaide

Kenji Takahashi

Shoji Hanamura

Ryuichi Izawa

Hideyuki Ono

Shusaku Nagahara

Shuhei Tanaka

Hajime Akimoto

Junichi Nakamura

Hideaki Yamamoto

Toshihisa Tsukada

Koichi Seki

Tadaaki Hirai

Isao Takayanagi

Toru Baji

Yukio Takasaki

Eiichi Maruyama

Masanobu Miyao

Masatada Horiuchi

Toshinori Otaka

Naoki Ozawa

Masao Tamura

Akihide Okuda

Shuusaku Nagahara

Yataro Yamashita

Shiya Ohba

Hajime Kinugasa

Syoji Hanamura

A system and method are disclosed to enlarge the sub-threshold current coefficient '&#x3b1;' of a reset transistor connected to a photodiode in an L-L (Linear Logarithmic) pixel sensor without modifying any semiconductor process parameters. In one embodiment, a coupling capacitor is introduced between the gate and source terminals of the reset transistor. The gate node of the reset transistor is kept floating and the change in its source voltage Vs is coupled to its gate voltage Vg by a certain rate with the help of the coupling capacitor. Thus, an effective change in (Vg-Vs) is made small, which is equivalent to enlarging the sub-threshold coefficient '&#x3b1;' In this manner, the signal gain in the logarithmic region of operation of the pixel sensor can be controlled by changing the coupling capacitance between the source and gate terminals of the reset transistor connected to the photodiode. The signal conversion gain in the logarithmic region is increased, but the gain in the linear region is unchanged. In one embodiment, the stray capacitance (which also affects the value of the enlarged &#x201c;&#x3b1;&#x201d;) present at the gate terminal of the reset transistor is externally controlled to achieve adaptive gain control of the output signal in the logarithmic region so as to obtain large output photo voltage swings even under varying light conditions. Because of the rules governing abstracts, this abstract should not be relied upon in construing the claims.

Linear-logarithmic pixel sensors and gain control circuits therefor

Embodiments provide a method and apparatus that achieve wide dynamic range operation of an image sensor. In an array of pixel cells, first charge is accumulated in a first subset of pixel cells during a first integration period and second charge is accumulated in a second subset of pixel cells during a second integration period. A length of the first integration period is different than a length of the second integration period, and the first and second charge are accumulated during a same frame and are read out.

Wide dynamic range operations for imaging

A wide dynamic range imager with a dual integration, selective readout operating method that requires only one readout chain. First signals from a row of pixels are digitized and stored into a memory after a first integration period. A flag is set and stored in the memory for each pixel that reached a threshold value during the first integration period. Second signals from the row are read after a second shorter integration period. If the pixel's corresponding flag bit was set, the second signal is stored (overwriting the first signal) and is subsequently used by processing circuitry to generate the appropriate pixel signal based on a full range signal and the second signal. Otherwise, the first signal is processed by the processing circuitry.

Wide dynamic range imager with selective readout

A solid-state imaging device includes a vertical CCD shift register for transferring electric charge. The electrode of the vertical CCD located nearest to the substrate is extended outside of the region of the vertical CCD to a region of a layer where isolation is required. The layer is thus imparted with two functions, that is, the function of the CCD electrode and that of the iolation electrode. An overflow transistor is also provided to discharge excess charge produced by high intensity light.

Solid-state imaging device

Vertical CCD registers constituting parts of an interline type CCD imaging device hold independently the signal charges transferred from photoelectric conversion elements and having different storage durations. Transfer of charge to the vertical CCD registers from the photoelectric conversion element is performed at least twice during one field period. The vertical CCD registers transfer the signal charges of different storage durations independent of one another.

A charge transfer type solid-state device incorporating a charge coupled device (CCD). In order to eliminate field after image and smear, at least two electrode pairs are provided in a vertical CCD shift register for transferring the signal charges stored in photoelectric conversion elements, the electrode pairs being disposed within the vertical pitch of the photoelectric conversion elements. P

Charge transfer type solid-state imaging device

This invention relates to an area imaging device having an array of picture elements formed of photodiodes and insulated-gate MOSTs which is vertically scanned by a shift register and horizontally scanned by a charge transfer device (CTD). The solid-state imaging device according to this invention has a transfer MOST provided between a vertical signal output line and a horizontal switch MOST, a resetting MOST connected to the junction between said transfer MOST and the horizontal switch MOST, and a mechanism for setting the vertical signal line at a reference potential just before signal transfer. The transfer MOST connected between the junction of the horizontal switch MOST and the resetting MOST and the vertical signal line is a double-gate MOST formed of a series connection of a transfer gate and another transfer gate. Therefore, the charges under the gate of the transfer MOST can be removed for fixed noise to be greatly reduced.

Herein disclosed is a method of reducing the vertical smears which are generated in a solid state image sensor including a plurality of vertical signal lines for transferring signal charges in a vertical direction and at least one charge transfer device for transferring the signal charges in a horizontal direction. The smear charges stored in the vertical signal lines and the signal charges generated in a photoelectric conversion element in response to an incident ray are inputted separately of each other for a horizontal blanking period to the charge transfer device for the horizontal transfer. During a tracing period, a smear voltage and a signal voltage are outputted separately of each other from said charge transfer device. The smear voltage adjusted is subtracted from the signal voltage to eliminate the smear component which has been mixed into the signal voltage.

Method of reducing vertical smears of a solid state image sensor

Disclosed is a two-dimensionally arrayed solid-state imaging device for a television camera having a photodiode array arranged at a photo-sensing section and a readout horizontal register constructed by a charge transfer device (CTD) such as a BCD, CCD or BBD. An inverter circuit is provided for each of the vertical signal lines. An input of the inverter circuit is connected to a vertical signal line drain of at least one transfer transistor arranged between the vertical signal line and the CTD, and an output of the inverter circuit is connected to a gate of the transfer transistor. Transfer efficiency is improved by the insertion of the inverter circuit and fixed pattern noise is substantially reduced by supplying bias currents.

High sensitivity solid-state imaging device

A solid-state imaging device is provided with picture elements which are each composed of a photoelectric conversion element and a MOS transistor as a switching element and which are arranged in the form of a matrix. A scanning mechanism sequentially scans the picture elements to sequentially read out photoelectric conversion signals. To eliminate smear and reduce parasitic capacitance, a high-impurity-concentration diffusion layer serving as an output terminal of the MOS transistor constituting the picture element is formed on an insulator layer for isolating the elements.

Disclosed is a solid-state imaging device wherein optical information of a number of photo-electric conversion elements arranged in a matrix is read into vertical signal lines by a vertical shift register and then the optical information on the vertical signal lines is horizontally scanned by a horizontal register of a charge transfer device. Bias charge storage means and quasi-signal sweep-out drains are disposed between the horizontal register and the vertical signal lines, and a bias charge input means is arranged in the horizontal register. In order to ensure high efficiency in transferring signals between the vertical lines to the storage means, the sweep-out drains and the charge transfer device, it is arranged for bias charges to be provided at each stage of transfer. Thus, bias charges supplied from the storage means are used to transfer charges from the vertical lines to the storage means. Similarly bias charges directly injected from the quasi-signal sweep-out drains are used to sweep out quasi-signals from the storage means to the quasi-signal sweep-out drains. Finally bias charges supplied from the bias charge input means of the charge transfer device are used to read signals from the storage means into the charge transfer device. By virtue of this, the sweep-out efficiency of the quasi-signals from the capacitances which supply the bias charges and a read-out efficiency of the signal charges are enhanced and a high quality of video signal is produced.

Solid-state imaging device with high quasi-signal sweep-out efficiency

In a solid state image pick-up device of the type comprising a first semiconductor layer including a photoelectric conversion element array, and vertical and horizontal switching elements adapted to select the photoelectric conversion elements, a second semiconductor layer including a horizontal shift register for selecting the horizontal switching elements, a third semiconductor layer including a vertical shift register for selecting the vertical switching elements, the first, second and third semiconductor layers are insulated from each other, and gate voltage V.sub.SMOS.L impressed upon a gate electrode of a not selected horizontal switching element is made to satisfy a relation V.sub.SMOS.L .gtoreq.V.sub.WPD +F.sub.FB where V.sub.WPD represents a potential of the first semiconductor layer, and V.sub.FB a flat band voltage beneath gate electrodes of the horizontal switching elements.

Solid state image pick-up apparatus

A solid-state imaging device comprises a plurality of photodiodes arranged in a matrix form in the same semiconductor substrate, horizontal and vertical switching elements for selecting the photodiodes, horizontal and vertical shift registers for supplying scan pulses to the horizontal and vertical switching elements, and an interlace circuit for simultaneously selecting two vertical gate lines to simultaneously read two picture element rows. A buffer circuit is inserted between the interlace circuit and the vertical gate lines for changing a potential level of one of the two selected vertical gate lines from a high level to a low level prior to changing the potential level of the other vertical gate line.

In a solid-state imaging device having a plurality of photodiodes which are arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements and a group of vertical switching elements which pick up the photodiodes, and a horizontal scanning circuit and a vertical scanning circuit which impress scanning pulses on the horizontal and vertical switching elements respectively, and having an interlaced scanning mechanism which picks up a plurality of vertical scanning lines by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows; a solid-state imaging device characterized in that said interlaced scanning mechanism includes insulated-gate field effect transistors for recovering voltage levels of the scanning pulses having undergone voltage drops due to the interlace switching elements.

Interlaced solid-state imaging device

A solid-state imaging device wherein a MOS sensor is employed for a photosensor part, a CTD shift register is employed for a read-out circuit, first and second transfer gates are connected between vertical signal output lines and the CTD, and a reset gate is connected between a juncture of the first and second transfer gates and a reset voltage line. A method is adopted in which signal outputs of a plurality of rows are transferred to the CTD in a horizontal blanking period, and signals of a plurality of rows are simultaneously read out in a horizontal scanning period. At the signal transfer, bias charges are dumped into the vertical signal output lines from the CTD, and mixed charges consisting of the bias charges and signal charges are transferred to the CTD. Thereafter, the signals are read out.

Growing community of inventors

Hachioji, Japan

Haruhisa Ando