Fujitsu Corporation

Haruhiko Ueno

Masayuki Ikeda

Shigeru Nagasawa

Naoki Shinjo

Kazushige Kobayakawa

Masami Dewa

Teruo Utsumi

Kenichi Ishizaka

Atsushi Takami

Tadao Amada

Masato Fukumori

Moriyuki Takamura

Tsutomu Tanaka

Takao Kato

Tsuyoshi Hashimoto

Hideki Sakata

Yoshihiro Kusano

Naoki Sueyasu

Yozo Nakayama

Koji Fujita

Masahito Kubo

Akitoshi Ino

Taku Komorida

Mari Masuda

Akikazu Nakagawa

Ken-ichi Ishizaka

A start test method executed by a system including a calculation device and a management device that manages failure information on the calculation device, the start test method includes storing, by a first processor included in the management device, a failure rate that has been calculated for each of parts of the calculation device based on the failure information received from the calculation device as performance information, associating with time information and a part of the calculation device; obtaining a failure rate of each of the parts at a time of start of the calculation device based on the performance information and a time when the calculation device is to be started; notifying the calculation device of the obtained failure rate; and executing, by a second processor included in the calculation device, a start test of the calculation device in accordance with the notified failure rate.

Start test method, system, and recording medium

An information processing device includes a processor configured to perform a diagnosis of hardware of the information processing device. The processor is configured to generate plural pieces of failure information. The plural pieces of failure information are classified into groups corresponding to different importance levels. The processor is configured to store the plural pieces of failure information in consecutive storage areas. The consecutive storage areas are divided into storage sections corresponding to the respective groups in order of importance level. The processor is configured to store first piece of failure information in a head of a second storage section in absence of free areas in first storage section. The first storage section is secured for a first group including the first piece of failure information. The second storage section is secured for a second group corresponding to a second importance level lower than the first importance level by one level.

Information processing device and method of storing failure information

A power measurement apparatus of a computer including logical units each including a CPU chip having CPU cores and a peripheral apparatus, a dedicated power supply apparatus for the respective CPU cores, and a common power supply apparatus for the peripheral apparatuses including: an output power generating unit that acquires output voltage and current of the dedicated power supply apparatus and generates output power thereof, a temperature acquiring unit that acquires a temperature of the CPU chip, an operation rate generating unit that generates an operation rate of the CPU core, a power consumption estimating unit which estimates power consumption of the peripheral apparatuses of the first and second logical units, and a power consumption generating unit that generates respective power consumption of the first and second logical units by summing up the output power of the dedicated power supply apparatus and the estimated power consumption of the peripheral apparatuses.

Power measurement apparatus and power measurement method

An information processing device, includes: a storage to store a program to be booted; a central processing unit to start a plurality of booting programs and read the program stored in the storage using a virtual address; a main memory to store the program based on a read instruction of the program; and a controller, including an address translator that translates a virtual address into a physical address, to read the program from the storage according to the read instruction, and write the read program in a plurality of discontinuous areas of the main memory on the physical address, wherein the central processing unit executes a start module which sets a virtual address space in the central processing unit and the controller before the plurality of booting programs are booted, and reads the written program from the main memory using the virtual address which is designated by the reading instruction.

Information processing device, information processing method, and recording medium storing control program

In a multi-processor system, each processor transmits a system time synchronous signal to another processor using hardware, and measures the propagation delay time of the signal. Then, the timer value of each processor is adjusted with the measured propagation delay time.

Multiprocessor clock synchronization with adjustment based on measuring propagation delay between a processor and a plurality of processors

A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address. Data is transferred from a first one of the plurality of processors to a second one of the plurality of processors by writing the data into the storage of the second processor according to the global virtual address or the local virtual address of the second processor, the second processor is notified of the global virtual address or the local virtual address of the transferred data, the notified global virtual address or the notified local virtual address is then translated into the real address which corresponds to the notified global virtual address or the notified local virtual address, data is read from the storage of the second processor to the second processor according to the translated real address, and the read data is calculated in the second processor.

Multiprocessor system and parallel processing method for processing data

A system information storage section stores access information showing attributes for accessing a storage peculiar to a processor and storages peculiar to other processors by relating the access information to data. The system information storage section stores space identifying information for identifying each of plural kinds of virtual spaces allocated according to applications of the storages. A plurality of address translation sections translate virtual addresses into real addresses, corresponding to the plural kinds of virtual spaces on the basis of the access information. A selection section selects any one of the plurality of address translation sections on the basis of the space identifying information. A transfer control section reads the data of the storage on the basis of the real address obtained by the selected address translation section and transfers the data to other processors together with the access information and the space identifying information.

Data transfer using local and global address translation and

A method and a processing apparatus for use in a parallel computer realizing a coordinate scheduling which does not degrade a throughput performance of a system. According to this invention, if a parallel process in execution gets into a parallel synchronization waiting state, the parallel process is deactivated so that allocation of the parallel process is inhibited, a process of another executable job is allocated, instead. If a setting condition is satisfied during the execution of another job, an interruption signal for a process in execution is generated to activate the parallel process in the parallel synchronization waiting state, thereby resuming allocation of this parallel process. This invention may be applied to a parallel computer system of a distributed main storage MIMD type which implements plural tasks in parallel by plural PEs.

Parallel process scheduling method in a parallel computer and a

A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.

Transfer processor including a plurality of failure display units

Data processing unit

A synchronous processing system including a plurality of processors and a communications network. Each processor includes a synchronization combination storage element, status storage element, control element, judging element and shifting element. The synchronization combination storage element stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element transmits the synchronous status information to all other processors. A judging element judges whether the group of processors are in synchronism based on the synchronization combination information and the transmitted status information. A processing shifting element shifts, when the group of processors are judged to be in synchronism, all the processors in the group to the next process of a program.

Synchronous processing method and apparatus for a plurality of

A transfer request queue control system for a parallel computer system includes a plurality of processing units each having a main storage storing instructions and data. An instruction processor reads the instructions from the main storage and executes the instructions. A transfer processor performs data transfers in packets, each comprising a header and body data and each data transfer comprising one or more packets. A network couples transmitting and receiving processing units, which are to perform a data transfer based on information included in the header of each packet, the header information being related to a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor performs parallel processing by making a data transfer between the main storage and the network in successive packets, depending on the attribute of the memory access. The transfer processor of one of the processing units comprises a transfer request queue comprising a list of headers of respective packets corresponding to each of plural requested data transfers, a managing part for managing a transfer queue valid flag which indicates validity of a transfer request of the transfer request queue and a control part for performing a data transfer in response to a data transfer request and based on the transfer queue valid flag.

Transfer request queue control system using flags to indicate transfer

A parallel processing system including a plurality of processing units each having a main storage storing instructions and data, an instruction processor reading the instructions from the main storage and executing the instructions, and a transfer processor for making a data transfer in units of a packet which is made up of a header and body data. The parallel processing system further includes a network coupling two processing units which are to make the data transfer based on information included in the header of the packet, where the header includes information related to at least a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor carries out a parallel process for each user process by making a data transfer between the main storage and the network in units of the packet depending on the attribute of the memory access. The transfer processor of at least an arbitrary one of the processing units includes a managing part for managing for each user process a transfer queue base address indicating a first address of a transfer queue in the main storage, a transfer queue write pointer indicating to which data transfer request of the transfer queue the instruction process has enqueued, a transfer queue read pointer indicating to which data transfer request of the transfer queue the transfer processor has finished the data transfer process, and a memory access virtual space.

Parallel processing system including instruction processor to execute

This invention relates to an abnormal packet processing system, and is directed to minimize processing of an abnormal packet during communication between a plurality of processing units by a receiving processor. This data processing system includes a plurality of processing units connected through an interconnection. At least one of the processing units is a transmitting processor which includes a unit for detecting an abnormality of a data packet during transmission of the data packet to a receiving processor; and a unit for adding abnormality report data to the data packet being transmitted and sending the data packet with the abnormality report data to the receiving processor, or, in the alternate, inhibiting transmission of the abnormal packet.

Abnormal packet processing system

Any two of multiple processor elements are coupled with each other via a data communication network that has a definite communication buffer length and includes multiple communication buffers. A packet having a header and body is created using processed data, and then transferred by a transmitting unit. After sending the processed data, the transmitting unit transmits dummy data, having a body which is longer than the communication buffer length in the data communication network, to the same receiving station as the one to which the processed data is transmitted. The transmitting unit then guarantees a processor element serving as a receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of the dummy data. When a transmitting end terminates transfer of the dummy data, the sending station can guarantee the termination of cache invalidation, which is performed by the processor element serving as a receiving station to attain the consistency of the contents of preceding storage data main storage and a cache memory.

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Kawasaki, Japan

Haruhiko Ueno