Nippon Precision Circuits Inc.

Seiko Npc Corporation

Haruhiko Otsuka

Eiichi Hasegawa

Hiroshi Kawago

Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuitreceives a control signal depending on an output of a phase comparison circuitfrom a control circuit, and comprises a first P-channel MOS transistor P, a second P-channel MOS transistor Pand a third P-channel MOS transistor P, and a first N-channel MOS transistor N, a second N-channel MOS transistor Nand a third N-channel MOS transistor N, and a first current source, a second current source, a third current sourceand a fourth current source. The transistor Pis turned on and off by an up-signal of the phase comparison circuit, and the transistor Nis turned on and off by a down-signal of it, and each of the transistor P, the transistor P, the transistor Nand the transistor Nis turned on and off on the basis of the control signal of the control circuit, an output signal from a VCO control terminalis input to a VCOthrough a low pass filterwhile causing current to flow through the charge pump circuit

Charge pump circuit reducing noise and charge error and PLL circuit using the same

In a quartz oscillation circuit, electric current flowing through a quartz oscillator is reduced. Resistors Rg and Rd are provided respectively in any of paths formed by an output terminal, a capacitance element Cd and a power supply terminal VDD of a CMOS inverter and any of paths formed by an input terminal, a capacitance element Cg and a power supply terminal VDD, thereby reducing a current flowing through a quartz oscillator. In particular, the total value of the resistors Rd and Rg is determined in a range of from 10&OHgr; to 320&OHgr;, thereby reducing a quartz current and obtaining a required negative resistance.

Quartz oscillation circuit and quartz oscillation integrated circuit device

A crystal oscillator circuit includes a CMOS invertor having an input terminal and an output terminal, a crystal resonator connected between the input terminal and the output terminal respectively at a first connection node and a second connection node, and a feedback resistor connected between the input terminal and the output terminal of the CMOS invertor. A first capacitor is provided between the first connection node and a power source terminal at a predetermined potential and a second capacitor is provided between the second connection node and a power source terminal at the predetermined potential. At least one resistor is disposed in series with at least one of the first capacitor and the second capacitor and has a resistance so as to limit a crystal current in the crystal resonator while maintaining negative resistance for stable oscillation. In an embodiment, a resistor is provided in series with each capacitor. Furthermore, an embodiment of the invention includes an integrated circuit permitting the above circuit structure with the crystal resonator and first and second capacitors accommodated external of the integrated circuit. Alternatively, the first and second capacitors may be accommodated on the integrated circuit.

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Tokyo, Japan

Haruhiko Otsuka