Kabushiki Kaisha Toshiba

Haruhiko Koyama

Mitsuhiro Noguchi

Daisuke Tsurumi

Minori Kajimoto

Yusuke Kohyama

Hiroyuki Kutsukake

Shinichi Watanabe

Tohru Ozaki

Yoshiko Kato

Kenji Gomikawa

Toyota Morimoto

Takayuki Toba

Akira Sudo

A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

Semiconductor memory device including a stacked gate having a charge storage layer and a control gate, and method of manufacturing the same

In one embodiment, a semiconductor device includes a resistor element and a stacked-gate type memory cell transistor. The resistor element includes a first conductive layer which is formed on a second conductive layer via a first insulating layer, and is electrically connected to an interconnect, the second conductive layer being on a substrate and in a floating state. The stacked-gate type memory cell transistor is on the substrate, and includes a floating gate formed of the same material as the second conductive layer.

Semiconductor device and method of manufacturing the same

A lack of exposure margin is avoided in a region, where an interconnection is required in a direction different from that of an interconnection of a region where an exposure condition is optimized. A semiconductor device According to an aspect of the invention includes a semiconductor substrate; an interlayer insulating filmthat is formed on the semiconductor substrate; a plurality of first interconnections, . . . that are formed in a first region on the interlayer insulating filmwhile complying with a first design rule, the first interconnections running along a specific direction; a plurality of second interconnections, . . . that are formed in a second region on the interlayer insulating filmwhile complying with a second design rule identical to the first design rule, the second interconnections running along the same direction with that of the first interconnections, . . . ; and a connection memberthat is formed in the interlayer insulating film, the connection member forming a desired interconnection pattern by electrically connecting at least the two second interconnectionsandthat should become an identical potential.

Semiconductor device and method of producing the same

A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Nonvolatile semiconductor memory device with reduced size of peripheral circuit area

A semiconductor memory device includes first and second element regions having a rectangular bent portion and a pair of straight line portions connected to both ends of the bent portions, respectively. The pair of straight line portions extends in an opposite direction each other along a first direction. A first element region is arranged in parallel with the second element region so that the first and second element regions are isolated by an element isolation region, and the first and second bent portions are arranged along a second direction in which the first direction intersects with the second direction at an acute angle. A select gate line connected to select transistors extends in the second direction. A plurality of word lines connected to the memory cells are arranged in parallel with the select gate line in an opposite side of the bent portions with respect to the select gate line.

Semiconductor memory device

In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.

Semiconductor device manufacturing method

A semiconductor memory device includes a well layer having a first conductivity type and formed in a semiconductor substrate, a block layer formed in a trench and formed of an insulating layer, a gate electrode formed on the semiconductor substrate apart from the block layer, a first diffusion layer having a second conductivity type, formed on a surface of the semiconductor substrate, and having a high impurity concentration region to a first depth from the surface of the semiconductor substrate, a second diffusion layer having the second conductivity type, formed on the surface of the semiconductor substrate on a side of the block layer away from the gate electrode, having a high impurity concentration region to a second depth greater than the first depth from the surface of the semiconductor substrate, and electrically connected to the first diffusion layer, and a contact connected to the second diffusion layer.

Semiconductor device with block layer and method of manufacturing the same

A first impurity diffusion area is formed in the semiconductor substrate at a bottom of the first trench formed in a surface of the semiconductor substrate. A second impurity diffusion area is formed in the surface of the semiconductor substrate, each have one end contacting a first side wall of the first trench, and each have the same conductive type as the first impurity diffusion area. A first gate electrode is provided on the first side wall between the first and second impurity diffusion areas with a gate insulating film interposed therebetween. A first ferroelectric film is provided on a first lower electrode, which is provided on the second impurity area. A first upper electrode is provided on the first ferroelectric film. A first interconnection layer is provided above the first upper electrode. A first contact plug electrically connects the first interconnection layer and first impurity diffusion area.

Semiconductor memory device and its manufacturing method

A method of fabricating a semiconductor device includes steps of forming a first insulating film, a conductive film, a second insulating film and a selected film in sequence on a substrate. Next, a first resist pattern is formed in a first region on the selected film by means of photo-lithography. The selected film is patterned by using the first resist pattern, after which the first resist pattern is removed. Next, a second resist pattern is formed in a second region on the surface of at least the second insulating film by means of electron beam lithography. The second insulating film is patterned by using the second resist pattern, after which the second resist pattern is removed. The conductive film is then patterned by using the patterned second insulating film as a mask. The selected film is provided with an etching characteristic substantially the same as that of the conductive film so that remaining portions thereof are removed during the conductive film patterning step.

Method of fabricating a semiconductor device

The present structure is characterized by the electrode of a trench capacitor of a DRAM and a periphery thereof. A trench is formed adjacent to an N type region in a substrate. An insulating film is formed on the side wall of this trench and only a part of the insulating film around the upper portion of the trench is removed, forming a window. An N type polycrystalline silicon film of a lower capacitor electrode is formed over a region from the bottom of the trench to below the window, and a capacitor insulating film is formed on this polycrystalline silicon film. A polycrystalline silicon film which becomes a first upper capacitor electrode is formed on the capacitor insulating film, filling the trench up to the lower edge of the window. A monocrystalline silicon film which becomes a second upper capacitor electrode is formed on the latter polycrystalline silicon film in such a way as to contact an N type region, filling the upper portion of the trench. An insulating film similar to a gate insulating film on the substrate is formed on the monocrystalline silicon film.

Growing community of inventors

Yokohama, Japan

Haruhiko Koyama