Kabushiki Kaisha Toshiba

Haruhide Kikuchi

Masahiro Baba

Ikuko Inoue

Eiji Sato

Masayuki Koizumi

According to one embodiment, a solid-state image sensing device includes a semiconductor substrate having a first and second surface, an insulating film covering an element on the first surface, a pixel array including pixels configured to photoelectrically convert light applied on the side of the second surface, contact regions in the semiconductor substrate, one or more through-electrodes respectively provided in the contact regions, and first pads provided on the side of the second surface to correspond to the respective contact regions. The first pad extends in a first direction from the contact regions toward the pixel array.

Solid-state image sensing device and camera

A multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M is described. The multiplied clock generating circuit comprising: a frequency divider circuit which is configured to generate a feedback clock signal by dividing the output clock signal by a factor M; a phase comparator circuit which is configured to receive the input clock signal and the feedback clock signal as generated by the frequency divider circuit, to compare the phase of the input clock signal with the phase of the feedback clock signal and to output a phase displacement signal indicative of the phase relationship between the input clock signal and the feedback clock signal; a comparator which is configured to receive the phase displacement signal, to count the output clock signal within each cycle of the feedback clock signal while the phase displacement signal is indicative that there is a phase displacement between the feedback clock signal and the input clock signal, to compare the numbers as counted in successive cycles of the feedback clock signal, and to output a delay time adjustment signal on the basis of the result of the comparison; and an oscillator circuit which is capable of controlling the output clock signal in the clock period thereof by an increment(s) of a predetermined delay time on the basis of the delay time adjustment signal and outputting the output clock signal as controlled.

Multiplied clock generating circuit

A booth decoder decodes A or &minus;A according to a booth algorithm, depending upon whether A&times;B or &minus;A&times;B should be multiplied. A partial multiplier/partial adder circuit,generates partial products of A&times;B or &minus;A&times;B following to a result of the decoding, and sequentially adds these partial products. Data C, or data made by inverting bits of C, is input to the partial multiplier/partial adder circuit,, depending upon whether C should be added or &minus;C should be added to the result of multiplication. Also the data C or data made by inverting bits of C are sequentially added by the partial multiplier/partial adder circuit,. A final adder circuit,executes final addition of these partial products, and adds 1 when &minus;C should be added. Thus, Z&equals;&plusmn;(A&times;B)&plusmn;C (the order of signs being variable) can be calculated.

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Yokohama, Japan

Haruhide Kikuchi