Siemens Aktiengesellschaft

Hartwig Bierhenke

Siegfried Birkle

Roland Rubner

Hermann Kniepkamp

Walter Kellner

Relief structures comprised of double lacquer layers on substrates already having relief structures for integrated semiconductor circuits are produced by applying a lower lacquer layer onto such substrate and which is composed of a material which does not cross-link or decompose due to radiation energy and which has only relatively slight sensitivity at the radiation energy dosage range utilized for structuring; applying an upper lacquer layer onto the lower lacquer layer and which upper layer is thinner relative to the thickness of the lower layer by a factor of at least 2 and is composed of a highly sensitive negative lacquer material; generating desired relief structures in the upper lacquer layer and removing those portions of the lower lacquer which are not covered by the upper negative lacquer layer.

Method of producing relief structures for integrated semiconductor

The invention relates to a charge coupled element in which electrodes with blocking properties, arranged in series, are located on a semiconductor member of gallium arsenide. The semiconductor member has a semi-insulating gallium arsenide substrate on which an n-conductive layer of gallium arsenide is formed, which n-conductive layer has a charge carrier concentration of 1.multidot.10.sup.15 through 5.multidot.10.sup.17 cm.sup.-3. The electrodes form a blocking transition with this n-conductive layer.

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Grafing, Germany

Hartwig Bierhenke