International Business Machines Corporation

Hartmut Ulland

Richard Allen Kelley

Thomas Schlipf

Kevin W Kark

Juergen Haess

William Wu Shen

Rolf B Hilgendorf

Volker W Zimmermann

Walter Heinrich Lipponer

Joseph Curtis Diepenbrock

Ingemar Holm

Udo Wille

Price Ward Oman

Gerhard Zilles

Russell W Lavallee

Rainer Zuehlke

Dieter Schutt

Frank J Pita

Helmut H Weis

Siegfried Neuber

Jurgen Hass

Guenter Hahn

Manfred Schwengler

Klaus Muenzner

The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention further enables bus arbitration during a first transmission since that the bus can be granted for a second transmission following the first transmission without wasting bus cycles. This is accomplished by determining the number of cycles remaining for the first transmission according to memory boundary and transmission packet boundary conditions.

I/O throughput by pre-termination arbitration

A memory interface between the storage controller and memory card of an S/390 system uses the S/390 Storage Protect (SP) Key as an indication or protocol of storage command acceptance by the memory card. When the SP key is returned, then the command is deemed to be accepted by the memory card and the key will be used by the processor for its storage validation in accordance with the S/390 architecture. In the event that the memory card detected an error associated with the command, it will then return an error response code via a memory status bus. The memory status bus is multiplexed to service the existing architected requirement as well as an indicator of handshaking between the memory controller and the memory card.

Memory card interface method using multiplexed storage protect key to indicate command acceptance

A method and system for the design verification of logic units capable of providing verification of a logic unit design prior to chip production. At least one test unit is coupled to a logic unit via an interface. The test unit includes a set of operations which are applied to the logic unit. The selection of test operations to be applied to the logic unit and the determination of the start times thereof are executed randomly and independently of each other. Thus, with the present method and system two parameters of the test operation generating event: the sequence of the test operations, and the temporal relationship between the test operations, are independently and randomly modified.

Method and system for the design verification of logic units and use in

The invention is related to hot plugging of an electrical circuit (1) into a separate non-quiesced signal net (6) in an active system (7), such as a digital or analog bus. The inventive solution proposes the addition of a preconditioning network (4) to precondition the electrical circuit (1) to be hot plugged by partially precharging the parasitic input capacitances (C.sub.c, C.sub.e, C.sub.m) of the electrical circuit (1) before hot plugging. The precharging of the parasitic input capacitances serves to minimize transient effects on the active system (7).

Precharge for non-disruptive bus live insertion

A device for storing and displaying graphic information having a storage unit for storing both blocks and rows of data and retrieving rows of data. The storage unit consists of two storage segments, with eight storage modules each, which can operate in an interleaved mode. This permits two-dimensional addressing which consists of distributing the individual elements of a data block over the various separately addressable modules of the storage unit so that no one module contains more than one element of the data block, and that all elements of the data block can be read out in one cycle through simultaneous access of all of the storage modules.

Device for storing and displaying graphic information

An improved method and apparatus for determining the speed and position values of a stepping motor for controlling or regulating the same. These values are derived from induced voltages within the bifilar windings of the stepping motor combined with voltages across and currents through the same bifilar windings. The speed values are derived from the amplitude of the induced voltages and the position values are derived from the zero transitions of the induced voltages. A desirable advance of the motor is distinguished from an undesirable oscillation of the motor by determining whether the induced voltages in the bifilar windings become zero simultaneously.

Method and apparatus for determining stepping motor parameters from

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Altdorf, Germany

Hartmut Ulland