Apple Inc.

Dialog Semiconductor Gmbh

Fujitsu Semiconductor Europe Gmbh

Hartmut Sturm

Jay B Fletcher

Sanjay Pant

Talbott Mead Houk

Fabio Rigoni

Bogdan-Eugen Matei

Siarhei Meliukh

Otto Schumacher

Nikola Jovanovic

Nathan F Hanagami

Floyd L Dankert

Wenxun Huang

Di Zhao

Olivier Girard

Kai Dieffenbach

Alessandro Molari

Ludmil N Nikolov

Tristan R Hudson

Seyedeh Maryam Mortazavi Zanjani

Joao Paulo Trierveiler Martins

Nicola Florio

Chad L Olson

John J Sullivan

Richard Landenbach

Marc Willam

Jonathan A Dutra

Joao Martins

The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.

Wakeup circuit

An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency.

Technique for smoothing frequency transitions during clock dithering

Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said sector comprising a plurality of said portions, and the memory having at least three said sectors each of which is adapted to be erased independently of the others; and control means operable to control erasing of the sectors, wherein: the control means is configured to store in a plurality of the sectors other than a target said sector erasure information concerning an erasure procedure, the erasure procedure involving erasing the target sector, so that such information in the sectors may be inspected to establish a suitable recovery procedure following an interruption event.

Electronic apparatus having non-volatile memory and method for controlling the same

A method for charging a battery is provided, wherein current pulses are supplied to the battery, wherein each pulse is followed by a rest period during which no current is supplied to the battery, and wherein the state of charge of the battery is determined during the rest period.

Device and method for charging a battery

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Germering, Germany

Hartmut Sturm