Siemens Aktiengesellschaft

Hartmut Schrenk

Wolfgang Pockrandt

An electronic debit card and a method for recharging the debit card include an integrated semiconductor circuit device having at least one address and control logic circuit and a non-volatile memory. At least one part of the nonvolatile memory is erasable, and memory locations of the region, provided for storing respective value units of the debit card, of the non-volatile memory each being divided up into subregions of different significance. Erasure of the memory locations is possible simultaneously only for all of the memory locations of a subregion of specific significance. Each subregion is capable of erasure only after a carry value has been written into a previously empty memory location of the subregion of the next highest significance. The value units of at least the memory locations of the most significant subregion in a release register of the debit card are assigned release values to be stored, which represent either a release state or a blocking state for the respectively assigned value state of the memory locations of the at least most significant subregion, and raising the card value of the debit card is possible only by changing a release value assigned to the value state of a memory location, from the blocking state into a release state.

Electronic debit card and method for recharging an electronic debit card

In a data transfer system having at least one terminal and at least one portable data carrier configuration, for example a chip card, and a method of recharging the portable data carrier configuration through the use of the terminal, an area of a non-volatile memory of the card representing a monetary value is subdivided into two value areas of which only one is activatable into a non-volatile state and the other can only be activated temporarily in each case. When the card is recharged, the new counter status is written into the value area which has initially only been activated temporarily. It is only after checking the correct writing that this value area is switched in such a way that it is activatable into a non-volatile state.

Data transfer system having a terminal and a portable data carrier

A method for preventing unauthorized data modification is carried out in a device, such as a chip card, having a nonvolatile memory, a central processing unit, and a program memory assigned to the central processing unit. A command is given to set a check bit in a check register being triggerable by the central processing unit, with a program for modifying data in a memory region of the nonvolatile memory. A check is made to determine if the command derives from a defined address region of the data modification program. The command is carried out by setting the check bit in the check register, if the command derives from the defined address region. A check is made for special permission for a data modification in a memory region of the nonvolatile memory. A check is made to determine if the check bit is set, if the special permission has been given. The data in the memory region is modified if a control bit is set. The check bit in the check register is reset and the permission to write is rescinded, after an allowed data modification, or if a data modification was not allowed, or if no check bit was set.

Method for preventing unauthorized modification of data in a device with

A debit card carries an integrable electronic circuit which is electronically debited. The circuit includes a nonvolatile, electrically erasable and writable memory operated as a multi-stage counter with counter stages. The circuit is provided with a nonvolatile, electrically erasable and writable check memory which has check memory regions associated with respective counter stages of the counter memory. The card is debited in that at least one of the memory cells of a memory is read out with at least two different weighting thresholds, and the counter memory is controlled as a function of the results obtained in that reading. The reading of the carry bit and the associated check bit allow to safely prevent against manipulation and the circuit may be realized at a very low expense.

Method and circuit configuration for debiting a debit card

In a method and circuit for protecting circuit configurations having an electrically programmable non-volatile memory used as a non-volatile counter, an access check is provided in the circuit configuration by comparison of a check code to be fed in with a secret code. Each counter bit is evaluated immediately after programming the counter bit. A protected function is disabled in dependence on the recognition of the counter bit as written. The reading level is set during the evaluation of a particular counter bit to be more-critical than in all of the later reading operations of the counter bit.

Method and circuit for protecting circuit configurations having an

A method for protecting secret code data stored in a data memory from analysis includes forming conclusions as to the content of the memory from signals at outputs of the memory, and limiting transfer of the code data from the data memory into a peripheral logic to a predetermined time period and an apparatus for carrying out the method.

Integrated circuit with an access-controlled data memory

A debit card includes at least one address and control logic circuit and a nonvolatile memory having a zone with memory locations provided for storing updated devaluation status of the debit card. At least part of the memory is electrically erasable and all of the memory locations of the zone of the nonvolatile memory can be read out and written upon bit by bit. A method and circuit for devaluation of a monolithically integrable electronic circuit of the debit card includes dividing the zone of the nonvolatile memory into partial zones each having a different value in the form of a multi-stage counter. A simultaneous erasure of the memory cells is permitted only for all of the memory cells of one partial zone of a given value. Erasure of each partial zone is permitted only after a transfer bit has been written into a previously unwritten memory cell of the partial zone of next-higher value. Writing-in is monitored with a logic circuit. An erasure of the partial zone of the highest value is permitted only under special conditions.

Method and circuit for manipulation-proof devaluation of EEPROMS

An integrated semiconductor circuit includes a substrate; a layer of electrical structures disposed in the substrate; conductor runs connected to the electrical structures; at least one electrically conducting surface element covering part of the electrical structures, part of the substrate and part of the conductor runs defining first conductor runs covered by the at least one surface element and second conductor runs; an insulating layer electrically separating the at least one surface element from first the conductor runs; and a passivating layer covering the substrate, the electrical structures, the conductor runs and the at least one surface element; the at least one surface element having at least the same thickness and the same chemical properties as the conductor runs; and the passivating layer being at least as thick above the at least one surface element covering the first conductor runs as above the second conductor runs.

Integrated semiconductor circuit

A monolithically integrated MOS circuit includes a memory area having electrically programmable storage cells (E.sup.2 PROM) with outputs, a potential source, at least one blocking circuit for connecting at least one of the outputs to the potential source, and a radiation sensitive sensor connected to the blocking circuit for controlling the connection of the outputs to the potential source.

EEPROM with protective circuit

Word-by-word electrically reprogrammable non-volatile memory includes an array in matrix form of memory cells containing respective storage transistors, the storage transistors having reading windows of different widths, respectively, in at least two subregions of the memory and a method of operation thereof.

Word-by-word electrically reprogrammable non-volatile memory and method

A method for controlling memory access to a user area and an initial code area of a main memory of a chip card includes carrying out an internal release procedure with a data comparison of an initial code from the initial code area and a data word from a terminal; firmly coupling addresses of the main memory and of a control memory to each other; marking several storage locations of the main memory as the initial code area with one control bit at a time in the control memory; marking a first code deposited in the associated storage location of the first code area as activated or deactivated with one further control bit at a time in the control memory; generating an initial release signal in a release procedure only if a storage location is addressed by an activated initial code and if agreement with the data word entered by the terminal prevails; and preventing generation of the initial release signal if a deactivated code word is addressed and/or if the respective first code does not agree with the data word, and an apparatus for carrying out the method.

Method for controlling memory access on a chip card and apparatus for

A process for carrying out a release operation for a user memory includes releasing a user function in dependence on a preceding data comparison of externally entered data with reference data stored in a code memory, continuously changing the content of a control memory ahead of every release, and monitoring the change through a comparison of the initial control memory content with the changed control memory content and apparatus for carrying out the method.

Release process for an access-controlled user memory and apparatus for

A monolithically integrated semiconductor circuit assembly includes a silicon substrate, an active layer with active electrical structures in a semiconductor circuit disposed on the silicon substrate, a passivating layer disposed on the active layer, at least one electrically conducting protective layer disposed on the passivating layer at least above the active electrical structures, and a casing disposed above the protective layer.

Monolithically integrated semiconductor circuit

A MOS inverter circuit includes a first supply voltage source, a second supply voltage source being higher than the first supply voltage source, a control MOS FET of the enhancement type, a first load MOS FET of the depletion type connected to the control MOS FET, a parallel circuit of a second load MOS FET of the depletion type and a third MOS FET, the parallel circuit being connected in series with the first load MOS FET, the third MOS FET having a controlled path connected to the first supply voltage source, and the first and second load MOS FET's having controlled paths interconnected in series and connected to the second supply voltage source.

MOS inverter circuit having two different supply voltages

Method for the functional testing of a memory being electrically programmable word by word and including storage cells having storage transistors with given reading window widths during normal operation, which includes reducing the width of the reading windows of the storage transistors during a functional test, as compared to the given width during normal operation, and an apparatus for carrying out the method.

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Haar, Germany

Hartmut Schrenk