International Business Machines Corporation

Hartmut R Schwermer

John David Wilson

Richard Allen Kelley

Douglas R Chisholm

Donall G Bourke

Charles B Perkins, Jr

Carl A Malmquist

John M Nelson

Roy Y Liu

Gregory D Float

Richard L Place

Rolf B Hilgendorf

Harry S Barowski

Hans-Werner Tast

Wolfram M Sauer

Werner Soell

Werner Dipl-Ing Söll

Rolf Dipl-Ing Hilgendorf

The present invention relates to data processing systems with built-in error recovery from a given checkpoint. In order to checkpoint more than one instruction per cycle it is proposed to collect updates of a predetermined maximum number of register contents performed by a respective plurality of CISC/RISC instructions in a buffer (CSB)() for checkpoint states, whereby a checkpoint state comprises as many buffer slots as registers can be updated by said plurality of CISC instructions and an entry for a Program Counter value associated with the youngest external instruction of said plurality, and to update an Architected Register Array (ARA)() with freshly collected register data after determining that no error was detected in the register data after completion of said youngest external instruction of said plurality of external instructions. Handshake synchronization for consistent updates between storage in an L2-cache () via a Store Buffer () and an Architected Register Array (ARA) () is provided which is based on the youngest instruction ID () stored in the Checkpoint State Buffer (CSB) ().

Checkpointing a superscalar, out-of-order processor for error recovery

A method for addressing internal instructions in an out-of-order processor is proposed, which allows for an efficient register renaming even in case internal instructions are issued to a multitude of window buffers. In this case, it is not clear how internal instructions that stem from one external instruction can be indicated as being 'related'. In the method proposed, a common instruction identifier is assigned to each of the internal instructions of a group of internal instructions representing an external instruction. Furtheron, an offset identifier is assigned to each of said internal instructions in order to be able to unambiguously identify each of said internal instructions. These two identifiers are used as a tag, in order to be able to resolve data dependencies. By use of the invention, exception handling, recovery of mispredicted branches, and committing related instructions corresponding to one external instruction is simplified.

Identification of related instructions resulting from external to

The invention provides an apparatus and a method for converting instructions of a code A to instructions of a code B. Said conversion is performed by obtaining rearrangement information, which corresponds to the instruction that is to be converted, from a table. Said rearrangement information is then used to rearrange the instruction elements of the initial instruction, in order to generate instructions of code B, which functionally corresponds to said initial instruction. Said rearrangement can be performed by multiplexing means, which use said instruction elements of the initial code A instruction as input, and which select one of said instruction elements, or the content of another register, and forward this selected data to the instruction that is to be generated. Said rearrangement information is directly used to control the selection performed by said multiplexers.

Dynamic conversion between different instruction codes by recombination

In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous 'handshaking' manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

Coupled synchronous-asychronous bus structure for transferring data

Method for performing inter-unit data transfer operations among a

In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.

Method for transferring information between main store and input output

Input output interface controller connecting a synchronous bus to an

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Stuttgart, Germany

Hartmut R Schwermer