Siemens Aktiengesellschaft

Hartmud Terletzki

Werner Reczek

Dominique Savignac

Heinz Hebbeker

Johannes Stecker

Johann Rieger

Xaver Guggenmos

Wolfgang Nikutta

Ioannis Chrysostomides

GTL output amplifier for coupling an input signal present at the input

A parasitic field effect transistor or a parasitic diode is formed in an integrated circuit. The parasitic element is formed by two doped regions of the same or opposite conductivity type and an insulating region therebetween. The doped regions are each connected to a respective terminal pad of the integrated circuit. To increase the ESD strength, the length of the insulating region in the lateral direction is greater than or equal to a length of the longest discharge path of the ESD protection structures connected to the terminal pads.

Integrated circuit with ESD protection

A fuse bank includes a fuse link being disposed above and insulated from a substrate. A first doped region in the substrate is a guard ring surrounding the fuse link. A second doped region has the same conduction type as the first doped region and is adjacent the first doped region. An insulation separates the second doped region from the first doped region. A high-impedance semiconductor component connects the first doped region to a first supply potential. The second doped region is connected to a second supply potential.

Fuse bank

A semiconductor component includes a semiconductor body having a terminal pad, a semiconductor function element, and an electrically conductive connecting line connecting the terminal pad to the semiconductor function element. A protective element for protecting against electrostatic discharge is connected between the terminal pad and the semiconductor function element. A first supply line for a first supply potential is connected to the semiconductor function element. A second supply line for the first supply potential is connected to the protective element and is electrically conductively connected to the first supply line. A clamp element is connected to the connecting line and to the first supply line, for limiting a voltage applied to the clamp element to a clamp value.

Semiconductor component with protective structure for protecting against

An integrated semiconductor circuit includes a semiconductor substrate. At least one first and at least one second potential rail respectively carry first and second supply potentials of the semiconductor circuit during operation. At least one input signal line has at least one input signal terminal and at least one output signal line has at least one output signal terminal and at least one additional line connected to the output signal terminal. At least one first circuit portion receives and processes input signals and at least one second circuit portion develops at least one output signal of the semiconductor circuit during operation of the semiconductor circuit. A configuration for protection against overvoltages has a first protection circuit for each input signal terminal being connected between a respective input signal terminal and a respective first circuit portion, and has a second protection circuit for each output signal terminal being connected to the additional line. Each protection circuit has a field oxide transistor, a field-controlled diode and a diffusion resistor. The potential rails each have a region adjacent at least one of the protection circuits. At least one of the potential rails has a tub-shaped protection structure disposed under the region. The protection structure is disposed in the substrate and is electrically conductively connected to a respective one of the potential rails.

Growing community of inventors

Munchen, Germany

Hartmud Terletzki