Intel Corporation

Samsung Electronics Co., Ltd.

University of California

Merck Patent Gmbh

Advanced Technology Materials, Inc.

Harsono S Simka

Adrien Lavoie

Juan E Dominguez

John J Plombon

Joseph Han

Ganesh Hegde

Ming He

Mark Stephen Rodder

Joon Goo Hong

Rebecca Park

Mark L Doczy

Valery M Dubin

Bryan Clark Hendrix

Jorge A Kittl

Daewon Ha

Rwik Sengupta

Mansour Moinpour

Sadasivan Shankar

David Michael Thompson

Daniel J Zierath

John D Peck

Mehdi Saremi

Thomas H Baum

Chongying Xu

Jong Hyun Lee

Jeffrey F Roeder

Kevin O'Brien

Jaehyun Park

Robert L Bristol

Florian Gstrein

Grant M Kloster

James M Blackwell

Tianniu Chen

Scott Bruce Clendenning

Byounghak Hong

Andrew C Kummel

Ramanan Chebiam

Kang-ill Seo

Patricio E Romero

Gregory T Stauf

Paul A Zimmerman

Inchan Hwang

Steven W Johnston

Chin-Chang Cheng

Michael G Haverty

Sang Hoon Ahn

Christopher D Thomas

Seungchan Yun

Jeonghyuk Yim

Chris Bowen

Gunho Jo

Ravindra Kanjolia

Michael Breeden

Anthony Dongick Lee

JaeHyun Park

Radek P Chalupa

Chihak Ahn

Seowoo Nam

Victor Wang

Juan E Dominquez

Damian Whitney

Iouri Lantassov

Terry T Buckley

Anand Durairajan

Harinath Reddy

Yung Bae Kim

Described are low resistivity metal layers/films, such as low resistivity ruthenium (Ru) layers/films, and methods of forming low resistivity metal films. Ru layers/films with close-to-bulk resistivity can be prepared on substrates using Ru(CpEt)+OALD, as well as a two-step ALD process using Ru(DMBD)(CO)+TBA (tertiary butyl amine) to nucleate the substrate and Ru(EtCp)+Oto increase layer/film thickness. The Ru layer/films and methods of preparing Ru layers/films described herein may be suitable for use in barrierless via-fills, as well as at M0/M1 interconnect layers.

Method of forming low-resistivity Ru ALD through a bi-layer process and related structures

Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

Nanosheet transistor devices and related fabrication methods

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods

Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.

Integrated circuit devices including a via and methods of forming the same

A single-substrate electroless (EL) plating apparatus including a workpiece chuck that is rotatable about rotation axis and inclinable about an axis of inclination. The chuck inclination may be controlled to a non-zero inclination angle during a dispense of plating solution to improve uniformity in the surface wetting and/or plating solution residence time across the a surface of a workpiece supported by the chuck. The angle of inclination may be only a few degrees off-level with the plating solution dispensed from a nozzle that scans over a high-side of the chuck along a radius of the workpiece while the chuck rotates. The angle of inclination may be actively controlled during dispense of the plating solution. The inclination angle may be larger at commencement of the plating solution dispense than at cessation of the dispense.

Methods and apparatus for electroless plating dispense

A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

Fully aligned via integration with selective catalyzed vapor phase grown materials

A method and a system for material design utilizing machine learning are provided, where the underlying joint distribution p(S,P) of structure (S)-property (P) relationships is explicitly learned simultaneously and is utilized to directly generate samples (S,P) in a single step utilizing generative techniques, without any additional processing steps. The subspace of structures that meet or exceed the target for property P is then identified utilizing conditional generation of the distribution (e.g., p(P)), or through randomly generating a large number of samples (S,P) and filtering (e.g., selecting) those that meet target property criteria.

Generative structure-property inverse computational co-design of materials

A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

Interconnects having long grains and methods of manufacturing the same

A method for characterizing a material for use in a semiconductor device and the semiconductor device using the material are described. The material has a unit cell and a crystal structure. The method includes determining a figure of merit (FOM) for the material using only forward conducting modes for the unit cell. The FOM is a resistivity multiplied by a mean free path. The FOM may be used to determine a suitability of the material for use in the semiconductor device.

Method of screening materials using forward conducting modes

A method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount.

Low resistivity interconnects with doped barrier layer for integrated circuits

Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a first conductive layer on a substrate and selectively forming a second insulating layer on the first insulating layer. The first insulating layer may include a recess, and the first conductive layer may be in the recess of the first insulating layer. The second insulating layer may include a first opening exposing a surface of the first conductive layer. The methods may also include forming a third insulating layer on the second insulating layer and the first conductive layer, forming a second opening extending through the third insulating layer and exposing the first conductive layer, and forming a second conductive layer in the second opening.

A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

Method and system for providing a reverse engineering resistant hardware embedded security module

In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

Semiconductor device and method for making the same

A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

Method and system for providing a reverse-engineering resistant hardware embedded security module

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Saratogo, CA, United States of America

Harsono S Simka