Texas Instruments Corporation

Harshit Moondra

Visvesvaraya Appala Pentakota

Neeraj Shrivastava

Nithin Gopinath

Viswanathan Nagarajan

Narasimhan Rajagopal

Jagannathan Venkataraman

Shagun Dusad

Eeshan Miglani

Srinivas Kumar Reddy Naru

Prasanth K

Chirag Chandrahas Shetty

Charls Babu

Shivam Srivastava

Abhinav Chandra

An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

Noise-shaping of additive dither in analog-to-digital converters

A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

Analog-to-digital converter (ADC) having linearization circuit with reconfigurable lookup table (LUT) memory and calibration options

In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

Calibration scheme for filling lookup table in an ADC

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Harshit Moondra