Apple Inc.

Harshavardhan Kaushikkar

Srinivasa Rangan Sridharan

Per Hakan Hammarlund

Gaurav Garg

James Vash

Steven R Hutsell

Brian P Lilly

Gurjeet S Saund

Lior Zimet

Lital Levy-Rubin

Sagi Lahav

Ramesh B Gunna

Sergio Kolor

Xiaoming Wang

Manu Gulati

Sukalpa Biswas

Steven John Fishwick

Gerard Richard Williams

Muditha Kanchana

Sridhar Kotha

Shinye Shiu

Benjamin K Dodge

Jonathan M Redshaw

Rohit Natarajan

Munetoshi Fukami

Shawn Munetoshi Fukami

Eran Tamari

Bikram Saha

Yu Zhang

Christopher D Shuler

Sergio V Tota

Erik P Machnicki

Gregory S Mathews

Deniz Balkan

Rohit Kumar Gupta

Prashant Jain

Jeff Gonion

Neeraj Parik

Odutola Oluseye Ewedemi

Wolfgang H Klingauf

Rong Zhang Hu

Samer Nassar

Kaushik Kannan

Jeonghee Shin

Yang Yang

Jeffry E Gonion

Wei-Han Lien

Jurgen M Schulz

Tal Kuzi

Lakshmi Narasimha Murthy Nukala

Michael Bekerman

Charles E Tucker

Tzach Zemer

Dany Davidov

Connie W Cheung

Nir Leshem

Mark Pilip

Seye Ewedemi

Anjana Subramanian

Yu Simon Zhang

Mukul A Joshi

Thejasvi M Vijayaraj

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Scalable system on a chip

Techniques are disclosed relating to memory controllers and rate-limited traffic. In some embodiments, an apparatus includes memory controller circuitry configured to satisfy different quality-of-service parameters for multiple different classes of request traffic. The apparatus may also include multiple agents configured to send requests to the memory controller circuitry, where the agents operate according to a rate limit for a first class of traffic. The apparatus may include cache circuitry. In some embodiments, based on an allocation in the cache circuitry for a read operation of the first class that causes an eviction from the cache circuitry, the control circuitry is configured to perform a write operation of evicted data: as the first class of traffic and without counting the write operation toward the rate limit for the first class of traffic. In contrast, the control circuitry may count other write operations of the first class of traffic toward the rate limit.

Handling eviction write operations caused by rate-limited traffic

A system may include multiple coherent agents, where a given coherent agent includes one or more caches configured to cache data. Memory controller circuitry may control one or more memory circuits from which the one or more caches are configured to cache data and maintain a directory that tracks which of the multiple coherent agent circuits is caching copies of a plurality of cache blocks and states of the cached copies in the multiple coherent agent circuits. A first agent may transmit a first request for a first cache block. The first agent may store, in request buffer circuitry, information corresponding to the first request then detect a second snoop from a second agent circuit to the first cache block. The first agent may absorb the second snoop, including to store information corresponding to the second snoop with the information corresponding to the first request in the request buffer circuitry.

Scalable cache coherency protocol

In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

Address hashing in a multiple memory controller system

A memory controller may include a dynamic arbitration scheme to dynamically vary arbitration factors of two or more traffic classes based on dynamic latency tolerance, requested and available bandwidths on an interconnect from source agents to memory controllers, and other dynamic and static factors.

Bandwidth-aware fabric traffic shaping

A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

Ensuring transactional ordering in I/O agent

Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

Communication channels with both shared and independent resources

An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

Configurable interface circuit

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

Multiple independent on-chip interconnect

Growing community of inventors

San Jose, CA, United States of America

Harshavardhan Kaushikkar