Globalfoundries Inc.

Harsh N Patel

Bipul C Paul

Joseph Versaggi

Structures for a non-volatile memory and methods for forming and using such structures. The structure includes a bitcell having a non-volatile memory element and a transmission gate. The transmission gate includes an n-type field-effect transistor and a p-type field effect transistor. The n-type field-effect transistor has a first drain region, a first source region, and a first gate electrode. The p-type field-effect transistor has a second drain region, a second source region coupled in parallel with the first source region, and a second gate electrode. The first drain region of the n-type field-effect transistor and the second drain region of the p-type field-effect transistor are coupled in parallel with the non-volatile memory element.

Non-volatile memory elements with multiple access transistors

Structures for a non-volatile memory and methods for forming and using such structures. A bitcell of the non-volatile memory includes a nonvolatile memory element and a field-effect transistor having a drain region coupled with the nonvolatile memory element, a source region, and a gate electrode. A word line is coupled with the gate electrode of the field-effect transistor, a bit line is coupled with the nonvolatile memory element, and a source line is coupled with the source region of the field-effect transistor. A power supply is configured to supply a negative bias voltage to the bit line in order to provide a first state for writing data to the nonvolatile memory element or to supply the negative bias voltage to the source line in order to provide a second state for writing data to the nonvolatile memory element.

Growing community of inventors

Clifton Park, NY, United States of America

Harsh N Patel