Intel Corporation

Vmware, Inc.

Nvidia Corporation

Harsh Kumar

Gunjeet D Baweja

George Gregory Hicken

Benjamin J Corrie

Yahya Cahyadi

Ian Hunter Gann

Nanda Kishore Krishna

Cheng-Feng Chang

Kun Fang

Abhijit Seal

Tim W Chan

Sachin Tiwari

Md Borhan Uddin

Nihar Mohapatra

Haluk Katircioglu

Vincent W Chang

Anubhab Majumdar

Anirudh B K

Sanjay R Deshpande

Adarsha Rao S J

A computer-implemented method, computer-readable medium and computer system to execute containerized applications includes initiating a Supervisor Cluster on top of a SDDC to support execution of containerized applications. A supervisor cluster namespace is created on the Supervisor Cluster. A storage policy is attached to the supervisor cluster namespace. Then, a control plane is bootstrapped, and containerized applications are executed in a virtual machine cluster using vSphere pods as the worker nodes in the virtual machine cluster.

Containerized application management

Various embodiments include techniques for processing memory operations in a computing system. The computing system includes a central processing unit (CPU) and an auxiliary processor, such as a parallel processing unit (PPU). The PPU can be divided into multiple partitions. Although the partitions are included in a single PPU, the CPU can track the partitions as if the partitions are independent devices rather than different portions of a single device. When two different partitions generate memory operations that access the same memory address in CPU memory address space, the two partitions employ two different data paths. The CPU can use path information for the two different paths to identify which partition generated each memory operation. As a result, the CPU can maintain data consistency and memory coherency in a system where a PPU is divided into multiple partitions.

Fully cache coherent virtual partitions in multitenant configurations in a multiprocessor system

An example method of configuring a cluster network for an application management system having virtual machines (VMs) executing on a virtualization layer in a cluster of hosts connected to a physical network, wherein the application management system is integrated with the virtualization layer, the method including: deploying, by a virtualization management server, a master server of the application management system prior to configuration of a cluster network that connects the VMs, the master server connected to the virtualization management server by a management network isolated from the cluster network; configuring, by the master server in cooperation with a network manager, the cluster network to connect the VMs; and connecting, by the master server in cooperation with the network manager, the cluster network to an edge node configured to support external ingress/egress for the cluster network.

Dynamic configuration of a cluster network in a virtualized computing system

Container images are fetched in a clustered container host system with a shared storage device. Fetching a first container image in a first virtual machine includes creating a first virtual disk in the shared storage device, storing an image of the first container in the first virtual disk, mounting the first virtual disk to the first virtual machine, and updating a metadata cache to associate the image of the first container to the first virtual disk. Fetching a second container image in a second virtual machine includes checking the metadata cache to determine that a portion of the image of the second container is stored in the first virtual disk, creating a second virtual disk in the shared storage device, adding a reference to the first virtual disk in a metadata of the second virtual disk, and mounting the second virtual disk to the second virtual machine.

Image file optimizations by opportunistic sharing

A system and method of performing an incremental backup process are disclosed. In certain aspects, the method comprises retrieving a first metadata associated with a previous backup process of a component from a backup location in a storage. The method further comprises passing the first metadata to the component for determining incremental backup data of the component corresponding to a difference between current data of the component and data of the component associated with the previous backup process. The method further comprises receiving information indicative of the incremental backup data from the component. The method further comprises receiving, from the component, a second metadata associated with the incremental backup process. The method also comprises storing the incremental backup data and the second metadata as associated with the incremental backup process.

Component aware incremental backup, restore, and reconciliation solution

An example method of configuring a cluster network for an application management system having a cluster of virtual machines (VMs) is described. The VMs execute on a virtualization layer in a cluster of hosts connected to a physical network, the application management system integrated with the virtualization layer. The method includes: receiving, at a first master server, a request to assign network ports of the cluster network to control VMs of the VMs, the control VMs executing master servers of the application management system and having first network interfaces connected to a management network isolated from the cluster network; provisioning, by cooperation of the first master server with a network manager, the network ports of the cluster network; and reconfiguring, by cooperation of the first master server with a virtualization management server, the control VMs with second network interfaces connected to the network ports of the cluster network.

An apparatus and method for branch prediction are disclosed. The branch predictor has four portions. The first includes a bimodal branch predictor in series with a local branch predictor; the second includes a global branch predictor. The first and second portions are in parallel and operate concurrently, and each provide an output received by the fourth portion. The third portion receives address data and selection data, and also provides output to the fourth portion. The fourth portion receives these outputs, and provides a branch prediction. The branch prediction is a selection of either the output from the first portion or the output from the second portion, based upon selection criteria received from the third portion.

Apparatus and method for branch prediction utilizing a predictor combination in parallel with a global predictor

An error correction code apparatus has a processor located (on-chip) L2 tag and error correction and detection, and an off-chip L2 data array and second error correction and detection, the chips connected by a data bus. For a write operation, ECC bits are generated and transmitted with data to the off-chip array. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed. For a read operation, stored ECC bits and data are retrieved from the off-chip data array and transmitted to the core processor. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed.

Error correcting code scheme

A branch prediction architecture is disclosed, having a branch predictor, a target address register, first and second multiplexors, a cache memory, and a trace cache. The branch predictor may advantageously be a series-parallel branch predictor, and alternatively may be a serial-BLG branch predictor or a choosing branch predictor. The first multiplexor receives an input from the target address register, and provides an output to the cache memory. The cache memory receives output from both the branch predictor and the first multiplexor, and provides an output to the second multiplexor. The trace cache receives the output from the branch predictor, and provides an output received by the second multiplexor. The second multiplexor, receiving input from both the trace cache and the cache memory, outputs branch predictions and instruction bundles.

Branch prediction architecture

The present invention provides an improved cache memory architecture with way prediction. The improved architecture entails placing the address tag array of a cache memory on the central processing unit core (i.e. the microprocessor chip), while the cache data array remains off the microprocessor chip. In addition, a way predictor is provided in conjunction with the improved memory cache architecture to increase the overall performance of the cache memory system.

Cache memory architecture with on-chip tag array and off-chip data array

The present invention provides a method and a data processing system for accessing a memory of a data processing system, the data processing system including a first and at least a second level memory for storing information. The method includes issuing a memory request to the first level memory, and issuing the memory request to the second level memory at substantially the same time the memory request is issued to the first level memory.

Cache memory with reduced latency

An apparatus and method for managing a memory is disclosed. A discharging unit discharges overcharged bit lines in memory. The discharging unit discharges the bit lines after a predetermined time after the last memory access. The discharging unit also discharges the bit lines after a microprocessor comes out of a low power mode.

Growing community of inventors

Fremont, CA, United States of America

Harsh Kumar