Sun Microsystems, Inc.

International Business Machines Corporation

Harsh D Sharma

Nadeem Eleyan

Hong Seok Kim

Howard L Levy

Christopher McCall Durham

Visweswara Rao Kodali

Nayon Tomsio

Michael J Lee

Douglas Ele Martin

Shervin Hojat

David Hogenmiller

Kong-Fai Woo

Sze Tom

Avi Liebermensch

A signal duration measurement system compares a known duration, Tof a test data signal with the duration, Tof a state of a signal under test. In one embodiment, if Tcompares favorably with Tthen the circuit generating the signal under test 'passes.' Otherwise the signal under test 'fails,' and a problem has been identified. Furthermore, in one embodiment, Tcan be selectively adjusted to more accurately measure TIn one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time. The signal propagation time can be adjusted by inserting varying delay elements into the signal path traversed by test data signal. The signal duration measurement system can be fabricated on-chip, thus making its use more practical. The signal duration measurement system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure.

On-chip measurement of signal state duration

A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.

Intelligent delay insertion based on transition

Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.

On-chip signal state duration measurement and adjustment

A circuit has been developed that reduces the effective strength of a keeper circuit during an interval in which at least one path of an evaluation circuit is sensitive to a keeper device. The keeper circuit includes a keeper gating device coupled to a keeper device that is responsive to a keeper control. The keeper device is sized to overcome leakage current in the evaluation circuit. In some configurations, the keeper circuit includes a weak keeper device that is minimally sized to overcome noise while the keeper device is effectively disabled. In some configurations, the reduction in effective strength of the keeper circuit occurs before arrival of the fastest signal coupled to a sensitive output path of the evaluation circuit and the effective strength is restored after arrival of the slowest signal coupled to the sensitive output path of the evaluation circuit.

Pulsed dynamic keeper gating

A method of transmitting and prioritizing signals is disclosed. Higher priority signals are switched while lower priority signals are delayed until the higher priority signals have completed switching. The method is used in networks where coupling and capacitance effects are possible.

Priority delay insertion circuit

The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.

On-chip PLL locked frequency determination method and system

Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.

Dividing and distributing the drive strength of a single clock buffer

Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.

Use of coupling capacitance to balance skew in a network

Provided are a method and a system to distribute clock signals in digital circuits to ensure that the multiple clock signals reach multiple loads associated with the digital circuit, concurrently. To that end, an off-chip set of clock paths, which includes one or more clock buffers, are connected between two sets of clock paths on an integrated digital circuit. The multiple clock signals are routed to the off-chip set of clock paths to reduce, or remove, propagational delay in multiple clock signals that arise from the propagation of the same through the on-chip clock paths. This is achieved by the clock paths of the off-chip set of clock paths having differing resistivities, differing lengths or both.

Method and a system to distribute clock signals in digital circuits

Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files retained in the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.

Method, system and computer product to translate electronic schematic files between computer aided design platforms

A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.

Domino to static circuit technique

A method for controlling delays in silicon on insulator circuits is disclosed. A semiconductor integrated circuit device comprises a first circuit and a second circuit. The first circuit includes multiple transistors, some of which have a floating body. In addition, the first circuit includes an input and an output. The second circuit is selectively coupled to a floating body of some of the transistors in the first circuit in order to control the delay of the output of the first circuit.

Method for controlling delays in silicon on insulator circuits

A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.

Method and device for the reduction of latch insertion delay

A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.

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Austin, TX, United States of America

Harsh D Sharma