At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Lucent Technologies Inc.

At+t Corp.

At&t Bell Telephone Laboratories, Incorporated

Harry T Weston

Adrian R Hartman

Gee-Kung Chang

Ya-Hong Xie

Robert J Bayruns

Clifford Alan King

James E Kohl

Philip W Diodato

Robert S Scott

Kwok K Ng

Michel Ranjit Frei

McDonald Robinson

Yiu H Wong

A device with at least one noise-sensitive element, at least one noise-generating element, and a porous silicon barrier in the substrate is disclosed. The porous silicon barrier isolates the noise-sensitive element from the signals coupled into the substrate by the noise-generating element. A process for making this device is also disclosed.

Integrated circuit device with isolated circuit elements

In an electronic system such as an integrated circuit having a number of destination loads such as logic gates, signal is distributed along typically a zero'th level (e.g., polysilicon) electrical transmission line from an input terminal to the destination loads. The characteristics of the signal arriving at the destination loads are improved by (1) inserting an added electrical transmission line, and (2) connecting various nodes of the added electrical transmission line through auxiliary active devices, such as inverters, to various nodes on the zero'th level electrical transmission line. In one attractive arrangement, each of the auxiliary active devices has an electrical-current-drive capability that increases monotonically with the number of nodes intervening between it and the input terminal of the added electrical transmission line.

Circuitry for delivering a signal to different load elements located in

An area saving dielectrically isolated semiconductor structure is disclosed which allows for the merger of a plurality of active devices, which share a common terminal, in a single dielectrically isolated (DI) island, or tub. In particular, an isolation groove is formed in the bottom of the DI tub and extends upwards toward the top surface of the semiconductor structure. The common diffusion region associated with the common terminal is located in the DI tub directly over the isolation groove. The isolation groove and common diffusion region thus separate the single DI tub into isolated sections, where a separate active device can be formed in each section. Isolation is achieved through the interaction of the groove with the common diffusion region to 'pinch off' the conductive channel between devices in the DI tub. In a preferred embodiment, an inverted V-shaped isolation groove is utilized so as not to complicate the fabrication process. In order to merge a large plurality of devices in a single DI tub, a plurality of isolation grooves may be utilized to divide the single DI tub into a number of separate isolated sections.

Inverted groove isolation technique for merging dielectrically isolated

A solid-state relay is combined with a control circuit to form a switch which is bilateral and linear through the origin, can withstand large current or voltage surges, and can be toggled either electrically or optically. The relay portion comprises either a pair of or two subsets of DMOS transistors, and the pair of transistors or selected ones of each subset cooperate to form a pair of oppositely poled thyristors. The control circuit provides well regulated turn-on and turn-off of the relay and provides good immunity against high voltage transients on the switch's main terminals. The control circuit also serves to limit the maximum voltage that is applied to the gate oxides of the transistors.

Switch utilizing solid-state relay

A frequency divider for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate or NAND gate, respectively, connected for delivering its output to an n-bit delay device, the NOR or NAND gate further connected for receiving the output of the delay device as feedback at one of its two-input terminals and for receiving the n-bit counting stream at the other of its two-input terminals. The output of the delay device is then a 2n-bit counting stream.

Self-correcting frequency dividers

A semiconductor structure including a pair of single-crystal semiconductor bulk regions (10.3, 12.2) of differing first and second bulk conductivities, respectively, for forming semiconductor circuits therein, is fabricated whereby each such region is electrically isolated from the other and from a rigid body (20) supporting these regions. The structure is formed by forming at a major surface of a single crystal semiconductor water (10) having the first bulk conductivity a bulk zone (12.1) having the second bulk conductivity, followed by the steps of (1) forming in the wafer (10) at the major surface (10.6) thereof a V-shaped groove (10.2) at the boundary of the bulk zone (12.1) using a crystallographic orientation dependent etch, in order to define the regions (10.3, 12.2) of differing conductivities, (2) forming a dielectric layer (15.1, 15.2) upon the walls of the V-groove and upon the exposed portion of the major surface, (3) forming a rigid body layer (20), such as polysilicon, upon the dielectric layer (15.1, 15.2), and (4) planarizing the exposed, opposed major surface of the single crystal medium down to the vertices of the V-grooves. The semiconductor circuits themselves can then be fabricated in the resulting mutually dielectrically isolated regions (10.3, 12.2).

Isolation process for high-voltage semiconductor devices

A semiconductor structure contains two interconnected gated diode switches in a common dielectrically isolated semiconductor tub. This structure functions as a bidirectional switch. A gate region physically located between the two switches provides electrical isolation to allow proper operation.

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New Providence, NJ, United States of America

Harry T Weston