Intel Corporation

Harry Q Pon

Robert E Larsen

Shawn C Sackman

Sanjay S Talreja

Ranjeet Alexis

Marcus E Landgraf

Wai Keung Tsang

A wireless device, such as a laptop computer or a cellular phone, may contain confidential information which may be secured by an internal security system. When the device is stolen, the user can provide a portion of a kill code to a wireless service provider. The wireless service provider provides its own portion of the kill code and combines it with the user's supplied code. Then, the service provider may transmit the combined kill code to the wireless device. Upon receipt, the wireless device may erase all confidential information on the device. In other embodiments, it may erase any unlocked block of memory. As still another alternative, the system may also, upon receipt of the combined kill code, disable the operating system.

Wireless device content information theft protection system

A circuit element that may generate or be affected by noise or electromagnetic interference may be substantially surrounded by one or more encircling plugs. The encircling plug may be closed by an interconnection layer. The plug may be grounded to reduce the electromagnetic interference or noise generated by or coupled to said passive circuit element.

EMI and noise shielding for multi-metal layer high frequency integrated circuit processes

An insulated bond wire to connect integrated circuits to each other or to substrates. Insulated bond wires may allow bond wires connecting integrated circuits and substrates to cross without shorting. Because bond wires may be crossed, integrated circuit assemblies with crossing bond wires may not need to be redesigned to avoid the wire crossings. In addition, insulated bond wires may also allow for closer spacing between bond wires due to reduced electronic interference between the wires. Closer spacing may allow for more input and output ports on an integrated circuit and thus increase its functionality.

Insulated bond wire assembly for integrated circuits

A low-power input buffer for a nonvolatile writeable memory is described. The low-power input buffer accepts input signals having one of a number of pairs of logic levels. The low-power input buffer provides output signals having a pair of logic levels that may differ from the logic levels of the input signal. The low-power input buffer comprises an inverter that receives an input signal, a circuit with a relatively low voltage drop, and a feedback pull-up device. The circuit with the relatively low voltage drop causes the low-power input buffer to accept input signals having one pair of logic levels while providing signals that may have a different pair of logic levels. The feedback pull-up device prevents the low-power input buffer from drawing leakage current. The low-power input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply output as the nonvolatile writeable memory. The low-power input buffer uses input signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

Self-configuring input buffer on flash memories

A low-power interface for nonvolatile writeable memory is described. The interface includes an input buffer and an output buffer. The input buffer receives input signals having one of a number of pairs of logic levels. The input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply as the nonvolatile writeable memory. The input buffer translates the input signals received to the signal level used by the nonvolatile writeable memory. The output buffer is coupled to the nonvolatile writeable memory and is coupled to a different power supply from the input buffer and the nonvolatile writeable memory. The output buffer translates the signals received from the nonvolatile writeable memory to the same signal levels as the input signal. The input buffer and output buffer utilize input/output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

Self-configuring interface architecture on flash memories

A high-speed output buffer for a nonvolatile writeable memory is described. The high-speed output buffer receives signals from the nonvolatile writeable memory having a pair of logic levels. The high-speed output buffer provides output signals having a pair of logic levels that may differ from the pair of logic levels of the signal received from the nonvolatile writeable memory. The high-speed output buffer comprises two inverters, a pull-up device, and a circuit with a relatively low voltage drop. The circuit with the relatively low voltage drop causes the high-speed output buffer to receive signals having one pair of logic levels while providing high-speed output signals having another pair of logic levels which may differ from the pair of logic levels of the received signal. The high-speed output buffer is coupled to a different power supply output from the nonvolatile writeable memory. The high-speed output buffer uses input and output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

1.8 volt output buffer on flash memories

An address transition detector receives one or more address signals. The address transition detector provides a transition detection signal in response to a transition of at least one of the address signals. A pulse generator is coupled to receive the transition detection signal and an environmental input. The pulse generator provides a control signal having a delay based upon an environmental input. The environmental control input may be based upon variables such as temperature, supply voltage, or process skew.

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Carmichael, CA, United States of America

Harry Q Pon