United Technologies Corporation

Ncr Corporation

Motorola Corporation

Harry N Gardner

Michael D Lahey

Debra S Harris

Michael J Barry

Charles R Gregory

Douglas W Garvie

Wayne R Gravelle

John P Petty

A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied in a memory circuit which includes a first memory cell and a second memory cell. The first and second memory cells receive a first input signal and a second input signal. The memory cells contain a logic circuit for producing a logic signal output driven by either a pullup or pulldown driver when the first and second input signals are of a desired logic state and produces a high impedance output if either input signal is not of their respective desired logic states. The memory cells also have sufficient nodal capacitance such that the output from the first or second memory cell will not be corrupted by an SEU in the logic circuit of either the first or second memory cell. The outputs of the first memory cell and second memory cell are further summed in analog fashion to produce a single output from the memory circuit. The summing of the output signals from the first and second memory cell prevents a single error in either memory cell from propagating to a next stage.

High reliability logic circuit for radiation environment

The present invention teaches an integrated circuit ('IC') gate array having improved reliability and increased immunity to deep space interference from electromagnetic radiation, photon energy, and charged particles. In one embodiment of the present invention, the gate array comprises a first and a second logical component, and a first and a second isolation transistor. Both first and second isolation transistors comprise an input, a biasing bus having a voltage potential, and an electrical contact for electrically coupling the biasing bus with the input. Moreover, the gate array comprises a redundant coupling for increasing the immunity of the gate array to charged particles, electromagnetic radiation and photon energy.

Gate array architecture and layout for deep space applications

An image sensing system utilizes a random access memory to provide image sensing and apply random access memory capabilities--data storage, refresh, nondestructive readout, etc.--to binary data representing the two-dimensional image. The random access memory can be used to effect a digital representation of the image or to provide electronic data, e.g., for optical character recognition.

Random access memory imaging system

An integrated circuit for sequentially receiving a plurality of digital character words produced in response to optical scanning of a bar coded label and a plurality of corresponding binary signals representing, respectively, validity, scanning direction, and timing of the digital character words includes first, second, third, and fourth sequentially located edges forming a rectangle. The integrated circuit includes input circuitry for receiving the digital character words and corresponding binary signals and further includes twelve shift registers for storing predetermined ones of the digital character words. Four frame counters and associated control circuitry responsive to the binary signals and the character words steer the incoming character words to predetermined ones of the shift registers. The integrated circuit outputs formatted character words to a digital processor system. A command decoder receiving commands from a digital processor system controls the outputting of valid, properly formatted digital character words from predetermined ones of the shift registers in response to an interrupt signal produced when a properly formatted character word is contained in one of the shift registers. The input circuitry is generally located adjacent the corner formed by the third and fourth edges. The frame counters and associated control circuitry are generally located substantially closer to the fourth edge than to the second edge. The twelve groups of shift registers are generally located between the frame state counters with their associated control circuitry and the second edge. The command decode circuitry is located adjacent the second edge.

Topography for integrated circuits pattern recognition array

A CCD (charge coupled device) RAM (random access memory) includes a plurality of 'rings' of serially connected CCDs in which digital information recirculates. A combinational decoder selects one of the plurality of rings by decoding a first group of binary address inputs. Each ring includes a plurality of input/output circuits coupled to associated 'taps', each tap being coupled between an input and an output of a CCD regeneration cell. An address addition circuit includes a counter which counts at the same rate that data shifts through each of the rings and has a plurality of taps spaced at the same intervals (numbers of intervening CCD cells) as the taps in each of the rings. The counter outputs are decoded to provide a first internal address corresponding to the location of a fictitious tag bit in a ring with reference to an initial reference bit in a ring.

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Colorado Springs, CO, United States of America

Harry N Gardner