Kilopass Technology, Inc.

Tc Lab, Inc.

Synopsys, Inc.

Winbond Electronics Corporation

Kilopass Technologies, Inc.

Nantero, Inc.

Klp International, Ltd.

Harry Luan

Valery Axelrad

Charlie Cheng

Bruce Lynn Bateman

Christophe J Chevallier

Jack Zezhong Peng

David Fong

Jianguo Wang

Colin Stewart Bill

Zhongshang Liu

Jein-Chen Young

Arthur Wang

Kenlin Huang

Chinh Vo

Tao Su

Pearl P Cheng

Thomas Rueckes

Yue-Song He

Glen Arnold Rosendale

Larry Lingjer Wang

Ting-Wah Wong

John M Callahan

Hemanshu T Vernenker

Kai-Cheng Chou

Michael David Fliesler

Fei Ye

Zhongshan Liu

Steve Wang

Chih-Chieh (Steve) Wang

Kaicheng Chou

A method of making stacked lateral semiconductor devices is disclosed. The method includes depositing a stack of alternating layers of different materials. Slots or holes are cut through the layers for subsequent formation of single crystal semiconductor fences or pillars. When each of the alternating layers of one material are removed space is provided for formation of single crystal semiconductor devices between the remaining layers. The devices are doped as the single crystal silicon is formed.

Formation of stacked lateral semiconductor devices and the resulting structures

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

Multi-layer random access memory and methods of manufacture

A method to fabricate a resistive change element array may include depositing a resistive change material over a substrate and forming a first insulating material over the resistive change material. The method may also include etching a trench in the resistive change material and the first insulating material and forming a cavity in a sidewall of the trench by recessing the resistive change material. The method may further include flowing a conductive material in the cavity and depositing a second insulating material in the trench.

Three-dimensional array architecture for resistive change element arrays and methods for making same

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

Multi-layer horizontal thyristor random access memory and peripheral circuitry

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

Multi-layer thyristor random access memory with silicon-germanium bases

Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

High density vertical thyristor memory cell array with improved isolation

Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.

3D stacked high-density memory cell arrays and methods of manufacture

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Thyristor volatile random access memory and methods of manufacture

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Harry Luan