Advanced Micro Devices Corporation

Globalfoundries Inc.

Harry Jay Levinson

Jongwook Kye

Khanh B Nguyen

Christopher F Lyons

Fei Wang

Scott Allan Bell

Lei Yuan

Chih Yuh Yang

Bruno M LaFontaine

Bruno M La Fontaine

Uzodinma Okoroanyanwu

Thomas Ingolf Wallow

Ryoung-han Kim

Adam R Pawloski

Calvin T Gabriel

Ivan Lalovic

Yuansheng Ma

Jeffrey A Schefske

Cyrus E Tabery

Jia Zeng

Obert Reeves Wood, Ii

Gilles Amblard

Soo Han Choi

Rene Wirtz

Amr Yehia Abdo

Anna Tchikoulaeva

Frank Tsai

Marina V Plat

Mahbub Rashed

Mammen Thomas

Christopher A Spence

Jason Eugene Stephens

Kouros Ghandehari

Jin Haeng Cho

Richard David Edwards

Anna Maria Minvielle

Xuelian Zhu

Stuart E Brown

Paul W Ackmann

Hidekazu Yoshida

Alden R Acheta

Fan Piao

Linda J Koyama

Thomas White

Bruno La Fontaine

A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate. A plurality of substantially parallel metal lines are disposed in the dielectric layer. The metal lines include active lines for routing signals to and from the devices, and dummy lines which do not route signals to and from the devices. Signal cuts are disposed in the active lines. The signal cuts define tips of the active lines. Assist cuts are disposed exclusively in the dummy lines and do not define tips of the active lines. The assist cuts are located proximate the signal cuts such that a first density of assist cuts and signal cuts in an area surrounding the signal cuts is substantially greater than a second density of signal cuts alone in the same area.

Assist cuts disposed in dummy lines to improve metal signal cuts in active lines of a semiconductor structure

Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.

Methods of design rule checking of circuit designs

One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.

Methods of generating circuit layouts that are to be manufactured using SADP routing techniques

Disclosed herein are various pellicles for use during extreme ultraviolet (EUV) photolithography processes. An EUV radiation device disclosed herein includes a reticle, a substrate support stage, a pellicle positioned between the reticle and the substrate support stage, wherein the pellicle includes an aerogel grid and a membrane formed on the aerogel grid, and a radiation source that is adapted to generate radiation at a wavelength of about 20 nm or less that is to be directed through the pellicle toward the reticle.

Pellicle with aerogel support frame

Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Self-aligned double patterning process for metal routing

A dense library architecture using an M0 hand-shake and the method of forming the layout are disclosed. Embodiments include forming first and second active areas on a substrate, at the top and bottom of a cell, separated from each other; forming first through third gate lines perpendicular to the active areas, where the first and third gate lines are dummy gates at the cell edges; forming trench silicide segments on each of the active areas, between the first, second, and third gate lines; forming first and second M1 metal lines between the first and second gate lines and the second and third gate lines, respectively; forming a M0 segment between the first and second active regions perpendicular to the M1 metal lines; forming a CB between the M0 segment and the second gate line; and forming a V0 from the first metal line to the M0 segment.

Middle of-line architecture for dense library layout using M0 hand-shake

A method of forming an ultra-regular layout with unidirectional M1 metal line and the resulting device are disclosed. Embodiments include forming first and second vertical gate lines, spaced from and parallel to each other; forming a M1 metal line parallel to and between the first and second gate lines; forming first, second, and third M0 metal segments perpendicular to the M1 metal line; connecting the first M0 metal segment to the M1 metal line and the second gate line; connecting the second M0 metal segment to the first gate line and the second gate line; connecting the third M0 metal segment to the first gate line and the M1 metal line; forming a first gate cut on the first gate line between the second and third M0 metal segments; and forming a second gate cut on the second gate line between the first and second M0 segments.

MOL architecture enabling ultra-regular cross couple

Methods for routing a metal routing layer based on mask design rules and the resulting devices are disclosed. Embodiments may include laying-out continuous metal lines in a semiconductor design layout, and routing, by a processor, a metal routing layer using the continuous metal lines according to placement of cut or block masks based on cut or block mask design rules.

Mask-aware routing and resulting device

A method involving identifying a pattern for an overall target cut mask to be used in patterning line-type features that includes a target non-rectangular opening feature having an inner, concave corner, decomposing the overall target cut mask pattern into first and second sub-target patterns, wherein the first sub-target pattern comprises a first rectangular-shaped opening feature corresponding to a first portion, but not all, of the target non-rectangular opening feature and the second sub-target pattern comprises a second rectangular-shaped opening feature corresponding to a second portion, but not all, of the target non-rectangular opening feature, the first and second openings overlapping adjacent the inner, concave corner, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, wherein at least one of the first and second sets of mask data is generated based upon an identified contact-to-end-of-cut-line spacing rule.

Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules

A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology

In one disclosed embodiment, the present method for semiconductor fabrication utilizing a cleaning substrate comprises loading a cleaning substrate capable of removing an undesirable particle from a semiconductor processing tool onto the tool, causing the undesirable particle to be attracted to the cleaning substrate, and unloading the cleaning substrate from the semiconductor processing tool. Following cleaning, the processing tool can be used for producing a lithographic pattern on a semiconductor wafer. In one embodiment, the cleaning substrate comprises an electret. In another embodiment, the cleaning substrate comprises an adhesive layer. The present method can be used without breaking vacuum, or otherwise altering the operational state of a processing tool. In one embodiment, the present method is used in conjunction with an exposure tool utilized for high resolution lithography, for example, an extreme ultraviolet (EUV) lithographic exposure tool.

Method for semiconductor wafer fabrication utilizing a cleaning substrate

One method disclosed herein involves, among other things, identifying a plurality of features within an overall pattern layout that cannot be decomposed using the SADP process, wherein at least first and second adjacent features are required to be same-color features, decreasing a spacing between the first and second adjacent features such that the first feature and the second feature become different-color features so as to thereby render the plurality of features decomposable using the SADP process, decomposing the overall pattern layout into a mandrel mask pattern and a block mask pattern, and generating mask data sets corresponding to the mandrel mask pattern and the block mask pattern.

Methods of generating circuit layouts that are to be manufactured using SADP techniques

Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules

Methodologies and an apparatus enabling a selection of design rules to improve a density of features of an IC design are disclosed. Embodiments include: determining a feature overlapping a grating pattern of an IC design, the grating pattern including a plurality of grating structures; determining a shape of a cut pattern overlapping the grating pattern; and selecting one of a plurality of rules for the feature based on the determined shape.

Cut mask aware contact enclosure rule for grating and cut patterning solution

Growing community of inventors

Saratoga, CA, United States of America

Harry Jay Levinson