Motorola Corporation

Harry J Geyer

Douglas G Mitchell

Francis J Carney, Jr

Ravinder K Sharma

James H Knapp

Marion I Simmons

James K Heckman

Setsuko J Cole

Robert W Helda

Ronald M Lahti

Renee M Gregg

A semiconductor device having a substrate support (22) and a method of forming the semiconductor device. A substrate (11) has conductive traces (12) and a bonding pad (13) on a bottom surface and conductive traces (14) and a semiconductor chip attach pad (17) on a top surface. The substrate support (22) has an aperture (23) and is coupled to the substrate (11). A semiconductor chip (31) is coupled to the semiconductor chip attach pad (17). The semiconductor chip (31) is covered by an encapsulating material (38) or a cap (41, 51) which provide protection for the semiconductor chip (31).

Semiconductor chip package and method of forming

A method of producing reliable bonds of a lead to a bump on a semiconductor chip is accomplished by controlling the amount of deformation of the lead and the bump during bonding. A differential amplifier is used to sense the deformation and stop the application of force to the lead and the bump when a desired amount of deformation of the lead and the bump is obtained.

Method and apparatus for controlled deformation bonding

An improved TAB bond is achieved by an apparatus for tape automated bonding, comprising a thermode having a bonding surface. A shield is attached around the bonding surface. The shield is designed so that a nonoxidizing gas may be distributed in a bonding space defined by a plurality of tape leads on a tape positioned below the shield and a bonding area of a semiconductor chip positioned below the tape and the plurality of tape leads. In the bonding position the flow of the nonoxidizing gas removes substantially all of an ambient air in the bonding space.

Apparatus for tape automated bonding

A module is described for use in data devices such as smart cards. The module consists of a contact carrier having contacts, an integrated circuit, and a base enclosing the integrated circuit. The base is formed to provide a groove around the perimeter such that when the device is formed, material from an intermediate layer will flow into the groove and secure the module to the card.

Data device module having locking groove

A titanium-tungsten-nitride/titanium-tungsten/gold (TiWN/TiW/Au) packaging interconnect metallization scheme is used to provide electrical contact to chip level interconnect metallization on a semiconductor substrate. The TiWN/TiW/Au packaging interconnect metallization scheme provides for good adhesion and barrier properties that withstand high temperatures and improve the reliability of the semiconductor chip. The TiWN layer provides good adhesion to the chip level interconnect metallization and the passivation layer. It also provides improved barrier properties to prevent the diffusion of other metal atoms through it. The TiW layer provides good adhesion to the gold metal layer. A gold bump may be electroplated to the gold layer and automatically bonded to a conductive lead of a tape in TAB packaging; or a wire bonded to the gold layer in conventional packaging.

Metallization scheme providing adhesion and barrier properties

A method for bonding which comprises the step of heating a bottom thermode to a temperature of approximately 150.degree. C. The bottom thermode is then pulse heated to approximately 350.degree. C. while a die and lead frame are disposed above the lower thermode. An upper thermode, which may remain unheated, is then lowered to cause contact between the lead frame and the contacts of the die. The lower thermode then returns to a temperature of approximately 150.degree. C. The pulse heating of the lower thermode lasts for approximately 1-3 seconds.

Bonding method and apparatus

Wire bonding is eliminated in the assembly of microelectronic devices, by a process involving the direct bonding of circuit electrodes to an unsupported metallic sheet-frame member having a plurality of inwardly extending leads. A single-step vibratory pressure welding technique is employed for the simultaneous bonding of all leads to a semiconductor integrated circuit chip. Lateral confinement of the leads during the bonding steps causes a buckling action to introduce a small but critical loop in each lead to ensure clearance between the lead fingers and the perimeter of the semiconductor chip, whereby electrical shorting is avoided. The loop also provides a structural flexibility in the leads, which tends to protect the bonding sites from excessive stresses. Subsequently, the first frame member including the bonded circuit is attached, preferably by resistance welding, to a second lead frame member of heavier gage and increased dimensions, suitable for connection with external circuitry. Excess portions of the first frame member are then removed, providing a completed assembly for packaging; e.g., plastic encapsulation or hermetic sealing, as in a ceramic-glass flat package.

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Phoenix, AZ, United States of America

Harry J Geyer