Taiwan Semiconductor Manufacturing Comp. Ltd.

Harry-Hak-Lay Chuang

Hung Cho Wang

Sheng-Huang Huang

Wei Cheng Wu

Sheng-Chang Chen

Wen-Tuo Huang

Hsin Fu Lin

Shih-Chang Liu

Wei-Cheng Wu

Kuo-Ching Huang

Jiunyu Tsai

Tsung-Hao Yeh

Tien-Wei Chiang

Chung-Jen Huang

Chung-Chiang Min

Wen-Chun You

Li-Feng Teng

Chien Hung Liu

Tsun Chung Tu

Yi Ching Ong

Chia-Shiung Tsai

Chern-Yow Hsu

Chang-Ming Wu

Kuo-Chyuan Tzeng

Chia-Sheng Lin

Chang-Chih Huang

Li-Jung Liu

Jun-Yao Chen

Ming-Che Ku

Ya-Chi Hung

Kuen-Yi Chen

Alexander Kalnitsky

Kuo-Chi Tu

Ming Chyi Liu

Chih-Yang Chang

Yao-Wen Chang

Yi-Chun Shih

Yuan-Tai Tseng

Sheng-Hung Shih

Tzu-Yu Chen

Chia-Hua Lin

Chun-Yang Tsai

Wei Chuang Wu

Fu-Chen Chang

Henry Wang

Yu-Ling Hsu

Chia-Hsiang Chen

Tsung-Hsueh Yang

Meng-Chun Shih

Ching-Huang Wang

Kuo-An Liu

Shih Kuang Yang

Ping-Tzu Chen

Hung-Cho Wang

Chia Yu Wang

Han-Yu Chen

Wan-Chen Chen

Chen-Pin Hsu

Yi-Hsuan Chen

Pai Chi Chou

Wei-cheng Wu

Shiang-Hung Huang

Yen-Yu Shih

Yuan-Jen Lee

Hsien Jung Chen

Shun-Kuan Lin

Chien Lin Liu

Yung Chun Tu

Chien Ta Huang

An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

Embedded flash memory device with floating gate embedded in a substrate

A dielectric isolation layer having a top surface may be formed over a substrate. A heater line, a phase change material (PCM) line, and an in-process conductive barrier plate may be formed over the dielectric isolation layer. An electrode material layer may be formed over the in-process conductive barrier plate. The electrode material layer and the in-process conductive barrier plate may be patterned such that patterned portions of the in-process conductive barrier plate include a first conductive barrier plate contacting a first area of a top surface of the PCM line, and a second conductive barrier plate contacting a second area of the top surface of the PCM line, and patterned portions of the electrode material layer include a first electrode contacting the first conductive barrier plate and a second electrode contacting the second conductive barrier plate.

Planarization-less phase change material switch

Some embodiments relate to a method of forming a redistribution layer (RDL) stack of a 3D integrated circuit stack. The method comprises removing a substrate form the first side of a first die to expose a first dielectric layer. A spiral trench is formed in the first dielectric layer with one end of the spiral trench directly over a through silicon via (TSV) beneath the first dielectric layer. A first barrier layer is formed along sidewalls of the spiral trench, the first barrier layer being thermally coupled to the TSV. A first conductive wire is formed within the spiral trench, separated from the first dielectric layer by the barrier layer.

Techniques for heat dispersion in 3D integrated circuit

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first deep trench isolation (DTI) structure in a substrate. A dielectric structure is over the substrate. An interconnect structure is in the dielectric structure. The interconnect structure includes a lower interconnect structure and an upper interconnect structure that are electrically coupled together. The upper interconnect structure includes a plurality of conductive plates. The plurality of conductive plates are vertically stacked and electrically coupled together. A back-side through substrate via (BTSV) is in the substrate and the dielectric structure. The BTSV extends from a conductive feature of the lower interconnect structure through the dielectric structure and the substrate. The conductive feature of the lower interconnect structure is at least partially laterally within a perimeter of the DTI structure. The BTSV is within the perimeter of the DTI structure.

Testing structure for an integrated chip having a high-voltage device

A semiconductor device and methods of fabrication thereof including a substrate, a doped well formed in the substrate, a transistor formed on the substrate, a dielectric material located over the doped well and the transistor and including interconnect structures extending through the dielectric material, the interconnect structures including a first set of interconnect structures electrically coupled to an active region of the transistor and a second set of interconnect structures electrically coupled to the doped well, an active memory cell electrically coupled to the active region of the transistor via the first set of interconnect structures; and a dummy memory cell electrically coupled to the doped well via the second set of conductive interconnect structures. The dummy memory cell and the second set of conductive interconnect structures may provide a low resistance pathway for plasma charge to flow to the doped well, thereby minimizing plasma induced damage to the transistor.

Embedded memory device with reduced plasma-induced damage and methods of forming the same

A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.

Energy harvest and storage device for semiconductor chips and methods for forming the same

The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes an inter-level dielectric (ILD) laterally surrounding a memory device. One or more sidewall spacers are arranged along opposing sides of the memory device. The one or more sidewall spacers have a bottom surface over a bottom of the memory device. An etch stop layer is disposed on the one or more sidewall spacers and along the opposing sides of the memory device. An upper interconnect is arranged directly over the memory device, a top surface of the one or more sidewall spacers, and an upper surface of the etch stop layer. The upper surface of the etch stop layer is vertically below a top of the memory device.

Etch stop layer for memory device formation

A magnetoresistive random access memory (MRAM) device is provided. The MRAM device includes a main magnetic tunnel junction (MTJ) array comprising a plurality of memory cells configured to store memory data and a reference MTJ array comprising a plurality of reference cells having MTJ structures. The MRAM device further includes a controller operatively associated with the main MTJ array and the reference MTJ array. The controller is configured to receive a gross resistance of the reference MTJ array being related to a strength of an external magnetic field, determine whether the external magnetic field is fatal based on the received gross resistance of the reference MTJ array and a pre-determined threshold, and provide notification indicating that the memory data stored in the main MTJ array is untrustworthy if it is determined that the external magnetic field around the MRAM device is fatal.

External magnetic field detection for MRAM device

Various embodiments of the present disclosure are directed towards an integrated chip including a memory cell overlying a substrate and comprising a top electrode. A sidewall spacer structure is disposed along sidewalls of the memory cell. The sidewall spacer structure comprises a first spacer layer on the memory cell, a second spacer layer around the first spacer layer, and a third spacer layer around the second spacer layer. The second spacer layer comprises a lateral segment adjacent to a vertical segment. The lateral segment abuts the top electrode and has a top surface aligned with or disposed below a top surface of the top electrode. A first conductive structure overlies the memory cell and contacts the lateral segment and the top electrode.

Method for MRAM top electrode connection

Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.

Techniques for MRAM MTJ top electrode connection

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.

Method for forming an integrated chip (IC) including forming a through substrate via (TSV) in an isolation structure formed in a first opening that formed in a metal substrate layer

Integrated chip (IC) having conductive TSV extended through SOI substrate comprising a semiconductor device layer, an insulating layer and a metal layer

A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.

Semiconductor packages and methods of manufacturing thereof

Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Method to embed planar FETs with finFETs

Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

Bonded wafer device structure and methods for making the same

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Zhubei, Taiwan

Harry-Hak-Lay Chuang