Taiwan Semiconductor Manufacturing Comp. Ltd.

Harry Hak-Lay Chuang

Ming Zhu

Bao-Ru Young

Lee-Wee Teo

Wei-Cheng Wu

Wei Cheng Wu

Kong-Beng Thei

Shih-Chang Liu

Carlos H Diaz

Chang-Ming Wu

Hui-Wen Lin

Hong-Dyi Chang

Chia-Shiung Tsai

Kuo-Cheng Ching

Chao-Cheng Chen

Hun-Jan Tao

Ryan Chia-Jen Chen

Yuan-Tai Tseng

Ru-Liang Lee

Ya-Chen Kao

Sheng-Chen Chung

Chiung-Han Yeh

Yuan-Sheng Huang

Po-Nien Chen

Chi-Hsun Hsieh

Han-Guan Chew

Pei-Chao Su

Eric Huang

Ting-Hua Hsieh

Hsien-Wei Chen

Shin-Puu Jeng

Hao-Yi Tsai

Syun-Ming Jang Jang

Chun-Hung Chen

Tien-Wei Chiang

Yi-Ming Sheu

Ming-Yuan Wu

Jin-Aun Ng

Cheng-Cheng Kuo

Yuh-Jier Mii

Chih-Yang Yeh

Yi-Ren Chen

Tzung-Chi Lee

Yu-Ying Hsu

Su-Chen Lai

Ching-Che Tsai

Chien-Hung Wu

Kai-Shyang You

Anson Wang

Han-Gan Chew

Lee-Wee Tao

Kuo Cheng Cheng

A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, and the first source region comprises a different material from the second source region.

Method of manufacturing semiconductor device

A semiconductor device includes a substrate with an isolation region surrounding a P-active region and an N-active region, a first gate electrode comprising a first metal composition over the N-active region, and a second gate electrode with a center portion over the P-active region and an endcap portion over the isolation region. The endcap portion includes a first metal composition, and the center portion includes a second metal composition different from the first metal composition, and the center portion and the endcap portion do not overlap. An inner sidewall of the endcap portion is substantially aligned with a sidewall of the isolation region.

Metal gate structure of a CMOS semiconductor device and method of forming the same

A complementary metal-oxide-semiconductor (CMOS) semiconductor device includes a substrate. The CMOS semiconductor device further includes an isolation region in the substrate. The CMOS semiconductor device further includes a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode includes a first function metal and a TiN layer doped with a first material. The CMOS semiconductor device further includes an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode includes a second function metal and a TiN layer doped with a second material different from the first material, a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate, and a portion of the TiN layer doped with the second material is between the portion of the P-metal gate electrode and the substrate.

Gate structure of a semiconductor device and method of making

A method of manufacturing a semiconductor structure includes forming a first dummy strip over a first active region and an isolation region of a substrate, removing a first portion of the first dummy strip from the first active region to form a first opening, filling the first opening with a first metal composition, removing a second portion of the first dummy strip from the isolation region to form a second opening, and filling the second opening with a second metal composition.

Fabrication method of a metal gate structure

A CMOS semiconductor device includes a substrate comprising an isolation region separating a P-active region and an N-active region. The CMOS semiconductor device further includes a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode includes a P-work function metal and a doped TiN layer between the P-work function metal and substrate. The CMOS semiconductor device further includes an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode includes an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate.

Gate structure of a semiconductor device

A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity. The first source region includes a different material from the second source region.

A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Embedded nonvolatile memory and forming method thereof

An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.

Circuit incorporating multiple gate stack compositions

A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first active region and a second active region divided by a shallow trench isolation (STI) region, a protective structure located on the STI region, a first semiconductor structure on the first active region, and a second semiconductor structure on the second active region of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a process of the high-k dielectric layer deposited before the formation of the first and second semiconductor structures.

Semiconductor device having protective structure over shallow trench isolation region and fabricating method thereof

A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal.

Semiconductor device with metal gate memory device and metal gate logic device and method for manufacturing the same

A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.

Method of forming gate structure of a semiconductor device

A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed.

System and method for a vertical tunneling field-effect transistor cell

Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.

Recessed salicide structure to integrate a flash memory device with a high &#x3ba;, metal gate logic device

A semiconductor device includes a semiconductor substrate, and first and second transistors over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors. The first and second transistors have the same nominal operating voltage. The first transistor has a higher threshold voltage than the second transistor. The second transistor has at least one of a source region or a drain region with higher charge carrier mobility than at least one of a source region or a drain region of the first transistor.

Semiconductor device and method of manufacturing

The present disclosure relates to a semiconductor integrated circuit which includes a substrate, a first patterned conductive layer, a first magnetic tunnel junction (MTJ) stack and a second MTJ stack. The first patterned conductive layer is over the substrate. The first MTJ stack, which is over the first patterned conductive layer, has a first size. The second MTJ stack, which is over the first patterned conductive layer, has a second size different from the first size.

Semiconductor integrated circuit and method of making the same

Growing community of inventors

Singapore, Singapore

Harry Hak-Lay Chuang