Taiwan Semiconductor Manufacturing Comp. Ltd.

Harry-Hak-Lay Chuang

Ming Zhu

Wei Cheng Wu

Bao-Ru Young

Hung Cho Wang

Shih-Chang Liu

Sheng-Huang Huang

Tien-Wei Chiang

Lee-Wee Teo

Chang-Ming Wu

Kong-Beng Thei

Chia-Shiung Tsai

Kuei-Hung Shen

Ya-Chen Kao

Cheng-Cheng Kuo

Ru-Liang Lee

Wen-Chun You

Wei-Cheng Wu

Jin-Aun Ng

Po-Nien Chen

Sheng-Chen Chung

Sheng-Chang Chen

Chi-Wen Liu

Chiung-Han Yeh

Chia-Hsiang Chen

Meng-Chun Shih

Ching-Huang Wang

Alexander Kalnitsky

Chin-Yi Huang

Chern-Yow Hsu

Huan-Just Lin

Mong-Song Liang

Ming Chyi Liu

Chih-Yang Chang

Chao-Hsiung Wang

Chih-Ping Chao

Chih-Yang Yeh

Carlos H Diaz

Wen-Ting Chu

Yu-Wen Liao

Pei-Ren Jeng

Chih-Tang Peng

Li-Feng Teng

Jen-Sheng Yang

Tong-Chern Ong

Ta-Wei Lin

Yuan-Tien Tu

Che-Cheng Chang

Cheng-Yuan Tsai

Ryan Chia-Jen Chen

Hsun-Chung Kuang

Kuo-Ji Chen

Chun-Hung Chen

Chang-Yin Chen

Yuan-Tai Tseng

Ming-Hsiang Song

Ching-Feng Fu

Yi-Jen Chen

Ming-Yuan Wu

Chen-Chin Liu

Jye-Yen Cheng

Chung-Chiang Min

Yung-Jung Chang

Shih-Ting Hung

Yu-Hsing Chang

Chung-Shi Liu

Chewn-Pu Jou

Yung-Chow Peng

Fu-Lung Hsueh

Yao-Wen Chang

Hsia-Wei Chen

Ming-Chyi Liu

Wen-Tuo Huang

Chia-Hua Lin

Shien-Yang Wu

Hua-Chou Tseng

Wei-Hang Huang

Tsung-Hsueh Yang

Alex Kalnitsky

Kuo-Cheng Ching

Tze-Liang Lee

Chao-Cheng Chen

Zhiqiang Wu

Yu-Der Chih

Ping-Wei Wang

Chii-Horng Li

Hun-Jan Tao

Shy-Jay Lin

Chung-Cheng Wu

William Joseph Gallagher

Chung-Long Chang

Yen-Ru Lee

Chun-Yi Lee

Chien-Wen Chen

Kuei Shun Chen

Chung-Jen Huang

Yuan-Sheng Huang

Tsung-Chieh Tsai

Chun-Jung Lin

Yuh-Jier Mii

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Polysilicon design for replacement gate technology

The present disclosure provides a semiconductor structure, including a memory region, a logic region adjacent to the memory region, a first magnetic tunneling junction (MTJ) cell and a second MTJ cell over the memory region, and a carbon-based layer over the memory region, wherein the carbon-based layer includes a recess between the first MTJ cell and the second MTJ cell.

Semiconductor structure and manufacturing method of the same

A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Semiconductor memory device and method for fabricating the same

The present disclosure provides a semiconductor structure, including an Nmetal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nmetal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)metal layer over the top electrode. The first width is greater than the third width.

Semiconductor structure and method of forming the same

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Structure and method for vertical tunneling field effect transistor with leveled source and drain

A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Method for fabricating a semiconductor device

A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

Semiconductor device having metal gate and poly gate

The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.

Memory device

Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Method to embed planar FETS with FINFETS

A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Semiconductor device

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.

Sidewall spacer structure for memory cell

An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.

MRAM memory cell layout for minimizing bitcell area

A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.

Via landing enhancement for memory device

A semiconductor feature includes: a semiconductor substrate; a dielectric structure and a semiconductor device disposed on the semiconductor substrate; an interconnecting structure disposed in the dielectric structure and connected to the semiconductor device; an STI structure disposed in the semiconductor substrate and surrounding the semiconductor device; two DTI structures penetrating the semiconductor substrate and the STI structure and surrounding the semiconductor device; a passivation structure connected to the semiconductor substrate and the DTI structures and located opposite to the interconnecting structure; and a conductive structure surrounded by the passivation structure, penetrating the semiconductor substrate and the STI structure into the dielectric structure, located between the DTI structures and electrically connected to the semiconductor device via the interconnecting structure.

Semiconductor feature and method for manufacturing the same

The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes a first surface, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a first magnetic field shielding, including a first portion proximal to the third surface of the semiconductor chip, wherein the first portion has a first height calculated from the mounting surface to a top surface, and a second portion distal to the semiconductor chip, has a second height calculated from the mounting surface to a position at a surface facing away from the mounting surface, wherein the second height is less than the first height, wherein the second portion has an inclined sidewall.

Package structure and method for fabricating the same

Growing community of inventors

Singapore, Singapore

Harry-Hak-Lay Chuang