Aeroflex Colorado Springs Inc.

Aeroflex Utmc Microelectronic Systems, Inc.

Utmc Microelectronic Systems Inc.

Aeroflex Utmc Microelectronics Systems, Inc.

Harry Gardner

David B Kerwin

Michael D Lahey

Stacia Patton

Debra S Harris

Peter Mikel Pohlenz

Radu Dumitru

A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.

Single event transient direct measurement methodology and circuit

A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an 'end cap' metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the 'birds-beak' region of the transistor, preventing further charge buildup. The &#x201c;end cap&#x201d; structure seals off the &#x201c;birds-beak&#x201d; region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

Total ionizing dose suppression transistor architecture

A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.

Radiation-hardened programmable device

An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Error correcting latch

Annular transistors are positioned with respect to the n-well diffusion region so that the active channels of the transistors are completely within the diffusion region, thereby avoiding the formation of the edges at the boundary between n active channel regions and adjacent field oxide region (the bird's beak region), which are susceptible to the effect of the ionizing radiation. The edgeless design of the gate arrays reduces the degradation of the transistors caused by the bird's beak leakage, while allowing for an unmodified commercial process flow for fabrication. An outer annular transistor and one or more inner annular transistors may be provided. The outer transistor may be used as an active transistor in the formation of logic circuits, or may provide isolation for the one or more inner transistors, which may be connected to form logic circuits. The design preferably includes a provision for readily disabling the radiation resistant system so the same design can be easily transformed into a non-radiation resistant design. Other electrical components such as a resistor may be formed with another annular gate electrode to isolate the component from the deleterious effects of ionizing radiation, as well.

Radiation resistant integrated circuit design

Functional and geometrical sub-components of logic circuits are defined and used in the design of integrated circuits to facilitate the transformation of an integrated circuit design for fabrication at foundries with different design rules.

Method for fabricating integrated circuits

A P-channel transistor is disclosed having P&plus; source and drain regions formed in a N&minus; well, which is formed in a P&minus; substrate. A third P&plus; region is provided that functions as a well tie. When the P-channel transistor is used as the pull-up transistor in a CMOS &ldquo;push-pull&rdquo; output buffer circuit, the P&plus; well tie prevents undesired current flow from the bus back to the positive voltage supply. This prevents potential damage to the power supply plane and any additional components connected thereto. In another aspect, the N&minus; well has formed therein both a P&plus; and N&plus; well tie. Additional switch circuitry is provided which allows for upper level programmability or selection of either one or both of the two well ties, depending upon the ultimate circuit configuration.

Method of programmability and an architecture for cold sparing of CMOS arrays

A method of manufacturing an integrated circuit including adjusting a parameter of the operation of the integrated circuit, such as power dissipation, after prototype testing by changing only one mask. If prototype testing indicates that the performance specification for power dissipation, for example, is not met, the power dissipation can be adjusted by changing the size of the active areas to change the channel width of the gates of the circuit, by changing the size of the patterns of the active area masks. To decrease power dissipation, the size of the active area is decreased. Only the active mask need be changed. Preferably, the active area around the original contacts are maintained so that the positions of the contacts need not be changed. Consequently, the mask for defining the position of the contacts and the masks for defining the metallization layers need not be changed. To increase power dissipation, the size of the active areas is increased. The values of other parameters may be changed, as well.

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Colorado Springs, CO, United States of America

Harry Gardner