Westinghouse Electric Corporation

Harry G Oehler

James R Cricchi

David S Herman

Described herein a technique for constructing a complementary MOS device on a sapphire substrate so that the surface of the device is planarized, the P-channel and N-channel devices are in substantially correct registration, the threshold voltage for the back-channel leakage effect inherent in sapphire substrate device to occur is increased, and the areas of gate oxidation are pseudo self-aligned so as to minimize overlap of the gate oxide with the source and drain regions.

High yield processing for silicon-on-sapphire CMOS integrated circuits

A memory sense circuit is described incorporating a number of field effect transistors for comparing the threshold voltage of two variable threshold transistors.

Sense circuit for use in variable threshold transistor memory arrays

A nonvolatile (MNOS) memory array using varactor boosted select signals is disclosed. The memory utilizes a varactor circuit to boost the row select during the erase and write modes of operation.

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Glen Burnie, MD, United States of America

Harry G Oehler