Advanced Risc Machines Limited

Arm Limited

Harry Edward Oldham

Dipesh Ishwerbhai Patel

Andrew John Sowden

Nicholas Andrew Salter

A data processing apparatus and method are provided for controlling level shifting. The data processing apparatus comprises a first component provided within a first voltage domain and operable to receive a first supply voltage, and a second component provided within a second voltage domain and operable to receive a second supply voltage. At least one of the first and second supply voltages are dynamically variable. The data processing apparatus further comprises an interface cell between the first and second voltage domains which is operable to receive a signal issued by the first component in the first voltage domain and destined for the second component. The interface cell comprises level shifting logic operable to convert the signal issued by the first component into a corresponding signal to be propagated to the second component in the second voltage domain. Further, bypass logic is provided which is operable in the event that the first supply voltage and second supply voltage are at the same voltage level to enable a bypass path around the level shifting logic such that the signal issued by the first component is propagated via the bypass path as the corresponding signal to the second component in the second voltage domain.

Level shifting in a data processing apparatus

A data memory includes a plurality of memory cells that are selectively operable during a memory read operation to generate a data signal indicative of data stored in that memory cell, and one or more sense amplifiers are connected to receive data signals from a plurality of the memory cells. An address decoder is responsive to a memory address supplied to the data memory for controlling one of said plurality of memory cells connected to each of the sense amplifiers to generate a respective data signal under the control of a first control signal. The data memory also includes circuitry for delaying the first control signal to generate a second control signal, and for energizing the one or more sense amplifiers for operation in response to the second control signal.

Data memory with sense amplifier and method of operation

A data memory includes a memory cell that operates to generate two complementary data outputs indicative of a data bit stored in the memory cell. First and second sense amplifiers set an output latch to a first output logic state in response to a first state of the complementary data output signals, and set the output latch to a second output logic state in response to a second state of the data output signals. One or the other, but not both of the sense amplifiers change state in response to the complimentary data outputs received thereby during a memory read operation.

Sense amplification in data memories

A data memory and a method of reading a data memory are described. Data words (Word0, Word1, Word2, Word3) are stored within the data memory within an array of memory cells arranged in columns and rows. A particular data word within a memory cell is accessed by activating a complete row (2) to output the data words within all columns of that row and then selecting the data word from the appropriate column with a data word selection multiplexer (6). An amplifier (8) is used to reduce the time taken for data signals read from the array to reach readable values. In order to save power, the amplifier is disabled during a second and subsequent successive reading operations from a row that has already been activated. Precharging of a output lines is also disabled for second and subsequent successive readings from a row.

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Cambridge, United Kingdom

Harry Edward Oldham