Hewlett-packard Development Company, L.P.

Jasper Design Automation, Inc.

Hewlett-packard Company

Harry David Foster

Chung-Wah Norris Ip

Lawrence Loh

Rajeev Kumar Ranjan

Kathryn Drews Kranen

Georgia Penido Safe

Nathan Dirk Zelle

Howard Wong-Toi

Claudionor José Nunes Coelho

Bradley Forrest Bass

Robert John Porter

An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Generalizing and inferring behaviors of a circuit design

To perform functional verification of a digital design that includes one or more datapaths, a formal verification system includes a datapath abstraction tool. The datapath abstraction tool detects a datapath in a circuit design and performs an appropriate abstraction of the datapath. The tool may also deduce datapath elements from identified ones as well as link the abstractions of particular datapath elements. The abstraction tool then passes the circuit design with the abstraction to the verification software to simplifying the formal verification process.

Managing formal verification complexity of designs with datapaths

A system and method for automatic verification of a test plan for a semiconductor device. The device is specified by a hardware description language (HDL) model or a formal description language model derived from the HDL model. A test plan tool and database are provided to capture test item definitions and identifications and a monitor generator is provided to generate monitors for detecting functional coverage during verification. An evaluator is provided to compare verification-events with test-plan items, to determine test item completeness and to update the test plan database.

System and method for evaluating functional coverage linked to a verification test plan

A method, and system in support thereof, of specifying hardware description language assertions targeting a diverse set of verification tools to provide verification of a logic design by the set of verification tools. The constraints and properties of the logic design are described in the HDL using one or more high-level assertion specification macros representative of the assertions of the logic design. The one or more assertion specification macros are stored as components within a specification macro library for later retrieval as needed. Upon reading original HDL source code containing assertion macro calls to the assertion specification macros, a specification macro processor accesses the definitions of the assertion macros stored, if contained within a definition library, and uses these definitions as templates to automatically write expansion HDL code into the HDL source code and to automatically store tool-specific HDL code into corresponding tool-specific modules libraries for later use by one or more verification tools. If definitions of one or more of the assertion macros are not contained with the definition library, they may be written as needed.

System and method for specifying hardware description language assertions targeting a diverse set of verification tools

An equivalence checking system and method efficiently determine whether different circuit models are functionally equivalent. The equivalence checking system first verifies the functional equivalence of a first circuit model to a second circuit model. In verifying this equivalence, the equivalence checking system produces mapping point pairs. The equivalence checking system utilizes these mapping point pairs in determining whether other models of the circuit are equivalent to the first model. Since the mapping point pairs are reused by the equivalence checking system, the number of new mapping point pairs needed to verify the functional equivalence of the other models is reduced or eliminated. Accordingly, the overall efficiency of the equivalence checking system is increased.

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Plano, TX, United States of America

Harry David Foster