Broadcom Corporation

Hrl Laboratories, LLC

Harry Contopanagos

Chryssoula Kyriazidou

Sissy Kyriazidou

Nicolaos Georgiou Alexopoulos

Reza Rofougaran

Christos Komninakis

Ahmadreza Rofougaran

Jacob Jude Rael

John Jacob Ottusch

Stephen M Wandzura

John F Visher

Vladimir Rokhlin

An unconditionally stable on-chip filter includes a filtering section and at least one negative resistance module. The filtering section is operably coupled to filter a signal and includes realizable integrated circuit passive components. The at least one negative resistance module is operably coupled to compensate for integrated circuit losses of the filtering section. The realizable integrated circuit passive components have values that are robust, in comparison to parasitic values, have minimal integrated circuit real estate, and provide realizable values for various integrated circuit manufacturing processes including CMOS technology.

Unconditionally stable filter

A high-Q on-chip inductor includes a primary winding and an auxiliary winding. The primary winding includes a first node and a second node. The auxiliary winding is operably coupled to increase a quality factor of the primary winding.

On-chip high Q inductor

An inductor circuit includes a magnetic interface generator that generates a magnetic interface at a center frequency f. The magnetic interface generator is a passive array of spirals that are deposited on one layer of a multi-layer substrate. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate layer that it is printed on, where the antenna is printed on a second layer of the multi-layer substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length Dof the spirals in the spiral array. The spacing S of the spiral array is chosen to project the magnetic interface to the second layer in the multi-layer substrate so as to effect performance of an inductor that printed on the second layer.

Inductor circuit with a magnetic interface

A magnetic interface generator generates a magnetic interface at a center frequency f. The magnetic interface generator is a passive array of spirals that are deposited on a substrate surface. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length Dof the spirals in the spiral array. In embodiments, the spiral array is one sub-layer in a multi-layer substrate. The spacing S of the spiral array is chosen to project the magnetic interface to another layer in the multi-layer substrate so as to improve performance of a circuit in the plane of the magnetic interface. For example, the magnetic interface can be used to increase the inductance of a printed inductor circuit, and to increase the gain and match of a microstrip patch antenna. Furthermore, the magnetic interface reduces the traverse electric (TE) and transverse magnetic (TM) surface waves in the plane of the magnetic interface, which reduces unwanted coupling between transmission lines.

Methods of generating a magnetic interface

A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1and 2nodes of the primary winding) that produces a large Q factor for an on-chip inductor.

Method of manufacturing high Q on-chip inductor

An on-chip inductor may be fabricated by creating at least one dielectric layer, creating at least one conductive winding on the at least one dielectric layer and creating: (1) a P-well layer having a major surface parallel to a major surface of the dielectric layer, (2) field oxide layer having a major surface parallel to a major surface of the dielectric layer, (3) P-well and field oxide layer, or (4) a poly-silicon layer having a major surface parallel to a major surface of the dielectric layer.

Method of manufacturing an on-chip inductor having improved quality factor

Unconditionally stable on-chip filter and applications thereof

An on-chip inductor and/or on-chip transformer includes at least one dielectric layer and at least one conductive winding on the at least one dielectric layer. The conductive winding has a substantially square geometry and has at least its exterior corners geometrically shaped to reduce impedance of the conductive winding at a particular operating frequency. Since the quality factor of an on-chip inductor is inversely proportional to the effective series impedance of an inductor at an operating frequency, by reducing the effective series impedance, the quality factor is increased.

On-chip inductor having a square geometry and high Q factor and method of manufacture thereof

Apparatus for generating a magnetic interface and applications of the same

An antenna includes a magnetic interface generator that generates a magnetic interface at a center frequency f. The magnetic interface generator is a passive array of spirals that are deposited on one layer of a multi-layer substrate. The magnetic interface is generated in a plane at a distance Z above the surface of the substrate layer that it is printed on, where the antenna in printed on a second layer of the multi-layer substrate. The distance Z where the magnetic interface is created is determined by the cell size of the spiral array, where the cell size is based on the spiral arm length and the spacing S between the spirals. The center frequency of the magnetic interface is determined by the average track length Dof the spirals in the spiral array. The spacing S of the spiral array is chosen to project the magnetic interface to the second layer in the multi-layer substrate so as to improve performance of the antenna that printed on the second layer. The magnetic interface can be used to increase the gain, matching, and bandwidth of a microstrip patch antenna, or other type of antenna.

Antenna with a magnetic interface

A computer program product, an apparatus, and a method for modeling equivalent surface sources on a closed, arbitrarily shaped object that result from the imposition of an arbitrary time-harmonic incident field (e.g., a radar wave) are provided. An object divided into by a plurality of patchesand parameters for the incident field and the properties of the objectare provided to the system. Next, the system produces a discretized representation of a well-conditioned boundary integral equation in the form of a well-conditioned matrix equation, modeling the interaction between the incident field and the object. The well-conditioned linear system is solved numerically to determine equivalent surface sources on the object. The equivalent sources may then be used to determine electromagnetic fields resulting therefrom. The invention provides improved computational efficiency as well as increased modeling accuracy by effectively reducing the numerical precision necessary.

Method and apparatus for modeling three-dimensional electromagnetic scattering from arbitrarily shaped three-dimensional objects

An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

Integrated circuit having oversized components

A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1 and 2 nodes of the primary winding) that produces a large Q factor for an on-chip inductor.

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Santa Monica, CA, United States of America

Harry Contopanagos