Taiwan Semiconductor Manufacturing Comp. Ltd.

Harry Chuang

Kong-Beng Thei

Sheng-Chen Chung

Mong-Song Liang

Chiung-Han Yeh

Ming-Yuan Wu

Chung Long Cheng

Chien-Liang Chen

Gary Shen

Mong Song Liang

Su-Chen Lai

Wen-Chih Yang

Chung-Long Cheng

Chen-Pin Hsu

Chii-Horng Li

Tzung-Chi Lee

Jin-Aun Ng

Jung-Hui Kao

Shun-Jang Liao

Ping-Wei Wang

Chun-Yi Lee

Chien-Wen Chen

Yi-Shien Mor

Wen-Huei Guo

Oscar M K Law

Chih-Tsung Yao

Bao-Ru Young

Ryan Chia-Jen Chen

Chien-Hao Chen

Chih-Tang Peng

Kuo-Tai Huang

Hao-Ming Lien

Jun-Lin Yeh

Kang-Cheng Lin

Hung-Chih Tsai

Ming-Jer Chiu

Maxi Chang

Heng-Kai Liu

Chung-Hau Fei

Manoj Achyutrao Joshi

Victor C Y Chang

Chun Ming Lin

Hung Chih Tsai

Chih Chieh Chen

Sheng Chen Chung

Kong Beng Thei

Chi Hsin Chang

Chung-Shi Liu

Kuo-Hua Pan

Hsin-Yi Lee

Yu Chao Lin

Shien-Yang Wu

Gwan Sin Chang

Cheng-Cheng Kuo

Chao-Hsiang Yang

Yung-Shun Chen

Yuan-Chen Sun

Yi-Hsing Chen

Hou-Ju Li

Keh-Chiang Ku

Wesley Lin

Shi-Bai Chen

Shang Y Hou

Yu-Tai Chia

Chung-Shi Chiang

Ssu-Yi Li

Ken Liao

Chen-Chia Wang

Ming-Hsin Li

Jen-Bin Hsu

Chien-Hau Fei

Chiun-Han Yeh

Chii-Horng Lee

Augus Tai

Charles Chen

Jeng-Long Huang

Ching-Han Yeh

Ssu-Yu Li

Wen-Chin Yang

Chung-Hua Fei

The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

Method of fabricating spacers in a strained semiconductor device

A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.

Process for controlling shallow trench isolation step height

A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

Wiring layout having differently shaped vias

A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The first gate and second gate could be associated with silicon-germanium (SiGe) source and drain regions to form p-type transistors. Next, a photoresist layer is deposited, and an opening of the photoresist layer is formed on the hard mask of the second gate. Then, the photoresist layer on the first and second gates is removed completely by etching back. Because there is no photoresist residue, the hard masks on the first and second gates can be removed completely afterwards.

Method for removing hard masks on gates in semiconductor manufacturing process

A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.

Integrated circuit metal gate structure and method of fabrication

An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.

Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors

A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

Integrating a first contact structure in a gate last process

A semiconductor device includes a semiconductor substrate, a source and a drain region formed on the semiconductor substrate, and a gate structure disposed on the substrate between the source and drain regions. The gate structure includes an interfacial layer formed over the substrate, a high-k dielectric formed over the interfacial layer, and a metal gate formed over the high-k dielectric that includes a first metal layer and a second metal layer, where the first metal layer is formed on a portion of the sidewalls of the gate structure and where the second metal layer is formed on another portion of the sidewalls of the gate structure.

Metal gate semiconductor device

A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.

SRAM devices utilizing strained-channel transistors and methods of manufacture

A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.

Photo alignment mark for a gate last process

A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.

Strained transistor with optimized drive current and method of forming

A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

Dishing-free gap-filling with multiple CMPs

The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.

Device scheme of HKMG gate-last process

A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Semiconductor device and method of fabricating same

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Hsin-Chu, Taiwan

Harry Chuang