3Com Corporation

Harrison Killian

Shayne Messerly

David M Arnesen

David Moore

Gerald A Wilson

Garn H Morrell

Brady V Brown

Jeff Allen Harrell

A system and method for providing a shortened DSP reset pulse to cause a modem to reset and enter a sleep mode as soon as possible after receipt of an external reset pulse issued by a host. A reset controller detects the external reset pulse, issues a separate reset pulse to the modem, monitors the modem's clock and then terminates the separate reset pulse after a prescribed duration. The prescribed duration is determined by the minimum time required by the DSP to reset. The invention is embodied in a modem connected to an external controller. The modem includes a DSP having a reset terminal and a clock. The DSP begins performing a reset upon a first signal applied to its reset terminal and causes the modem to enter a sleep-mode after a second signal is applied to its reset terminal. The external controller is capable of transmitting an external signal. The reset controller in the modem has a counter and an output node. The counter is connected to the clock and provides a counter output signal upon receipt of a predetermined number of cycles of the clock. The counter initiating generally concurrent with receipt of the external signal. The output node is connected to the reset terminal of the DSP and to the output counter. The output node provides a first signal to the DSP generally concurrent with receipt of the external signal and a second signal generally concurrent with receipt of the counter output signal.

System and method in a modem for providing a shortened reset pulse upon receipt of an external reset pulse

The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.

System and method for data pacing

The high throughput UART to DSP interface (UDIF) maintains UART functionality while integrating dual Transmit (Tx) and Receive (Rx) FIFO buffers that are optimized for more efficient interaction with their respective I/O processors. The portion of the interface design interacting with the DSP, the UDIF, provides several unique Status, Informational, and Control registers that lower the DSP overhead required for many of the basic modem functions. The UDIF design also performs parity add, parity strip, and character echo functions, traditionally performed at a high overhead cost by the DSP. These functions are more efficiently preformed by hardware implementations than by the software routines executed by the DSP. More burdensome command functions like escape, AT, and flow control commands can also be implemented through hardware implementations to reduce processor overhead.

High throughput UART to DSP interface having Dual transmit and receive FIFO buffers to support data transfer between a host computer and an attached modem

In a system having an DSP, an ASIC and a memory, in which the ASIC generates a number of different competing interrupts for the DSP to service, the ASIC has an interrupt request control module which automatically provides the DSP with a vector pointing to the memory location of the interrupt service routine for the currently pending interrupt request having the highest priority of all pending requests. The DSP reads this vector and uses it to access the interrupt service routine in the memory. Reading of this vector causes the interrupt request to be de-asserted, which causes the next highest priority pending interrupt request to become the highest priority pending interrupt request. As a result, a new vector is presented for the next read by the DSP.

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Kaysville, UT, United States of America

Harrison Killian